Contact plugs and methods forming same
A method includes forming a transistor, which includes forming a dummy gate stack over a semiconductor region, and forming an Inter-Layer Dielectric (ILD). The dummy gate stack is in the ILD, and the ILD covers a source/drain region in the semiconductor region. The method further includes removing the dummy gate stack to form a trench in the first ILD, forming a low-k gate spacer in the trench, forming a replacement gate dielectric extending into the trench, forming a metal layer to fill the trench, and performing a planarization to remove excess portions of the replacement gate dielectric and the metal layer to form a gate dielectric and a metal gate, respectively. A source region and a drain region are then formed on opposite sides of the metal gate.
1. A device comprising:
a semiconductor region;
a gate stack on the semiconductor region, wherein the gate stack comprises;
a gate dielectric; and
a metal-containing layer, wherein the gate dielectric comprises a first portion on a sidewall of the metal-containing layer, and a second portion overlapped by the metal-containing layer;
a laminate low-k liner on a first sidewall of the gate stack;
a gate spacer comprising a sub layer, wherein the sub layer comprises:
an inner sidewall in direct contact with the laminate low-k liner; and
an outer sidewall opposite to the inner sidewall, wherein a bottom end of the outer sidewall is in direct contact with the semiconductor region;
a source/drain region adjacent to the gate stack;
a source/drain contact plug over and electrically coupling to the source/drain region;
a high-k dielectric contact spacer encircling the source/drain contact plug; and
a source/drain silicide region between the source/drain region and the source/drain contact plug, wherein the high-k dielectric contact spacer extends lower than a top surface of the source/drain silicide region.
2. The device of claim 1 , wherein the laminate low-k liner comprises two sub layers formed of different materials.
3. The device of claim 2 , wherein each of the two sub layers has a bottom in physical contact with the semiconductor region.
4. The device of claim 2 , wherein both of the two sub layers comprise silicon and nitrogen.
5. The device of claim 1 , wherein the gate spacer further comprises:
an L-shaped layer comprising a horizontal leg and a vertical leg connecting to the horizontal leg, wherein the vertical leg contacts the sub layer; and
an outer spacer overlapping the horizontal leg, wherein the outer spacer contacts the vertical leg to form a vertical interface.
6. The device of claim 5 further comprising:
a contact etch stop layer comprising:
a vertical portion in direct contact with an additional outer sidewall of the outer spacer; and
a bottom surface in direct contact with a top surface of the semiconductor region.
7. The device of claim 1 , wherein the laminate low-k liner comprises silicon, carbon, and nitrogen.
8. The device of claim 7 , wherein the laminate low-k liner comprises SiOCN.
9. The device of claim 1 , wherein the high-k dielectric contact spacer has a first edge contacting a second edge of the source/drain silicide region.
10. The device of claim 1 further comprising a gate contact plug comprising:
a first metal layer formed of a same material as a first addition metal layer of the source/drain contact plug; and
a second metal layer over a bottom portion of the first metal layer, wherein the second metal layer is formed of a same material as a second additional metal layer of the source/drain contact plug.
11. A device comprising:
a replacement gate stack;
a laminate low-k dielectric liner directly on a sidewall of the replacement gate stack, wherein the laminate low-k dielectric liner comprises a first sub layer and a second sub layer, with the first sub layer and the second sub layer comprising different materials;
a dielectric spacer comprising a first sidewall contacting a second sidewall of the laminate low-k dielectric liner to form a vertical interface;
a source/drain region on a side of the replacement gate stack;
a source/drain silicide region over and contacting the source/drain region;
a source/drain contact plug over and contacting the source/drain silicide region; and
a high-k dielectric contact spacer encircling the source/drain contact plug, wherein the high-k dielectric contact spacer extends lower than a top surface of the source/drain silicide region.
12. The device of claim 11 , wherein the first sub layer comprises silicon and nitrogen.
13. The device of claim 12 , wherein the second sub layer comprises silicon, oxygen, carbon, and nitrogen.
14. The device of claim 11 , wherein both of the first sub layer and the second sub layer comprise pores therein.
15. The device of claim 11 further comprising:
a gate contact plug over and contacting the replacement gate stack; and
a high-k gate spacer encircling the gate contact plug.
16. The device of claim 15 , wherein the high-k gate spacer and the first sub layer comprise same elements, with the first sub layer comprising pores to have a low-k dielectric constant.
17. An integrated circuit device comprising:
a semiconductor region;
a gate stack on the semiconductor region;
a source/drain region adjacent to the gate stack and extending into the semiconductor region;
a source/drain silicide region on top of the source/drain region;
a source/drain contact plug over and contacting the source/drain silicide region; and
a high-k dielectric contact spacer encircling the source/drain contact plug, wherein the high-k dielectric contact spacer extends lower than a top surface of the source/drain silicide region.
18. The integrated circuit device of claim 17 , wherein the high-k dielectric contact spacer comprises SiOCN.
19. The integrated circuit device of claim 17 further comprising a laminate low-k dielectric liner on a sidewall of the gate stack, wherein the laminate low-k dielectric liner comprises a sub layer comprising SiOCN, with the sub layer comprising pores therein.
20. The integrated circuit device of claim 19 further comprising:
a gate spacer contacting the laminate low-k dielectric liner to form a vertical interface, wherein the gate spacer comprises an L-shaped layer, with a vertical leg of the L-shaped layer contacting the laminate low-k dielectric liner.