IP Library › Granted Patent US 11,317,042
Granted Patent B2
US 11,317,042 · App. 17/183,366 · Granted Apr 26, 2022

Image sensor apparatus and processing circuit capable of preventing sampled reset/exposure charges from light illumination as well as achieving lower circuit costs

Inventors: Kuan Tang (Hsin-Chu, TW); Yi-Cheng Chiu (Hsin-Chu, TW); Jui-Te Chiu (Hsin-Chu, TW)
Assignee: PixArt Imaging Inc.
H04N5/3559H01L27/14612H01L27/14643H04N5/3532
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Quick Facts
Patent No.
US 11,317,042
App. No.
17/183,366
Granted
Apr 26, 2022
Kind
B2
Abstract

An image sensor apparatus includes a pixel array having pixel units each including an image sensor cell and a processing circuit. The processing circuit includes a bias transistor, second floating diffusion node, first switch unit, signal transfer capacitor, reset transfer capacitor, second switch unit, and third switch unit. Bias transistor is coupled between first and second floating diffusion nodes and has control terminal coupled to bias voltage. First switch unit is coupled between first and second floating diffusion nodes. Second switch unit is coupled between second floating diffusion node and signal transfer capacitor. Third switch unit is coupled between second floating diffusion node and reset transfer capacitor. Signal transfer capacitor is selectively coupled to second floating diffusion node. Reset transfer capacitor is selectively coupled to second floating diffusion node.

Claims (40)

1. An image sensor apparatus capable of operating under a global shutter mode and a rolling shutter mode, comprising:

a pixel array comprising a plurality of pixel units, a pixel unit comprising:

an image sensor cell, comprising:

a photodiode;

a first floating diffusion node;

a transfer transistor, coupled between the photodiode and the first floating diffusion node, having a control terminal coupled to a transfer control signal;

a reset transistor, coupled between a reset voltage and the first floating diffusion node, having a control terminal coupled to a reset control signal; and

a specific row select transistor, having a first terminal coupled to the first floating diffusion node, a second terminal coupled to an output end of a processing circuit of the pixel unit, and a control terminal coupled to a specific row select control signal of the rolling shutter mode to dynamically turn on/off the specific row select transistor when the image sensor apparatus operates under the rolling shutter mode and not coupled to the specific row select control signal of the specific row select transistor when the image sensor apparatus operates under the global shutter mode; and

the processing circuit, comprising:

a bias transistor, coupled between the first floating diffusion node and a first reference level, having a control terminal coupled to a bias voltage;

a second floating diffusion node;

a first switch unit, coupled between the first floating diffusion node and the second floating diffusion node;

a signal transfer capacitor, coupled to the first reference level;

a reset transfer capacitor, coupled to the first reference level;

a second switch unit, coupled between the second floating diffusion node and the signal transfer capacitor; and

a third switch unit, coupled between the second floating diffusion node and the reset transfer capacitor;

wherein when the image sensor apparatus operated under the global shutter mode, the signal transfer capacitor is selectively coupled to the second floating diffusion node via the second switch unit, and the reset transfer capacitor is selectively coupled to the second floating diffusion node via the third switch unit.

2. The image sensor apparatus of claim 1 , wherein when the image sensor apparatus operated under the global shutter mode, a reset charge signal at the first floating diffusion node is stored into the reset transfer capacitor when the first switch unit is closed, the second switch unit is open, and the third switch unit is closed.

3. The image sensor apparatus of claim 2 , wherein the reset charge signal stored by the reset transfer capacitor is transferred to the second floating diffusion node when the first switch unit is open, the second switch unit is open, and the third switch unit is closed.

4. The image sensor apparatus of claim 1 , wherein when the image sensor apparatus operated under the global shutter mode, an exposure charge signal at the first floating diffusion node is stored into the signal transfer capacitor when the first switch unit is closed, the second switch unit is closed, and the third switch unit is open.

5. The image sensor apparatus of claim 4 , wherein the exposure charge signal stored by the signal transfer capacitor is transferred to the second floating diffusion node when the first switch unit is open, the second switch unit is closed, and the third switch unit is open.

6. The image sensor apparatus of claim 1 , wherein the image sensor cell is coupled to the processing circuit via a stacked pixel level connection channel; when the image sensor apparatus operated under the global shutter mode and the bias transistor is turned on and become conductive, the bias transistor is used to clear or reset a residual voltage level in the stacked pixel level connection channel; and, when the image sensor apparatus operated under the global shutter mode and the bias transistor is turned off, at least one charge signal at the first floating diffusion node is transmitted via the stacked pixel level connection channel to the second floating diffusion node.

7. The image sensor apparatus of claim 1 , wherein when the image sensor apparatus operates under the rolling shutter mode, the first switch unit is closed, the second switch unit is closed, and the third switch unit is closed, to make charges at the signal transfer capacitor and reset transfer capacitor be discharged to a ground level through the bias transistor.

8. The image sensor apparatus of claim 1 , wherein when the image sensor apparatus determines to read out a reset/exposure charge signal from the image sensor cell, the specific row select transistor is turned on to be closed according to the row select control signal to make an exposure charge signal or a reset charge signal at the first floating diffusion node be transmitted to the pixel unit's output end through the specific row select transistor.

9. A processing circuit disposed within a pixel unit further having an image sensor cell, the processing circuit being coupled to the image sensor cell of the pixel unit in a plurality of pixel units of a pixel array in an image sensor apparatus capable of operating under a global shutter mode and a rolling shutter mode, the image sensor cell having a specific row select transistor and a first floating diffusion node which is selectively coupled to a photodiode, the specific row select transistor being turned on when the image sensor apparatus operates under the rolling shutter mode, and the processing circuit comprises:

a bias transistor, coupled between the first floating diffusion node and a first reference level, having a control terminal coupled to a bias voltage;

a second floating diffusion node;

a first switch unit, coupled between the first floating diffusion node and the second floating diffusion node;

a signal transfer capacitor, coupled to the first reference level;

a reset transfer capacitor, coupled to the first reference level;

a second switch unit, coupled between the second floating diffusion node and the signal transfer capacitor; and

a third switch unit, coupled between the second floating diffusion node and the reset transfer capacitor;

wherein the signal transfer capacitor is selectively coupled to the second floating diffusion node via the second switch unit, and the reset transfer capacitor is selectively coupled to the second floating diffusion node via the third switch unit; and, when the image sensor apparatus operates under the rolling shutter mode, the first switch unit is closed, the second switch unit is closed, and the third switch unit is closed, to make charges at the signal transfer capacitor and reset transfer capacitor be discharged to a ground level through the bias transistor.

10. The processing circuit of claim 9 , wherein when the image sensor apparatus operates under the global shutter mode, a reset charge signal at the first floating diffusion node is stored into the reset transfer capacitor when the first switch unit is closed, the second switch unit is open, and the third switch unit is closed.

11. The processing circuit of claim 9 , wherein the reset charge signal stored by the reset transfer capacitor is transferred to the second floating diffusion node when the first switch unit is open, the second switch unit is open, and the third switch unit is closed.

12. The processing circuit of claim 9 , wherein when the image sensor apparatus operates under the global shutter mode, an exposure charge signal at the first floating diffusion node is stored into the signal transfer capacitor when the first switch unit is closed, the second switch unit is closed, and the third switch unit is open.

13. The processing circuit of claim 12 , wherein the exposure charge signal stored by the signal transfer capacitor is transferred to the second floating diffusion node when the first switch unit is open, the second switch unit is closed, and the third switch unit is open.

14. The processing circuit of claim 9 , wherein the image sensor cell is coupled to the processing circuit via a stacked pixel level connection channel.

15. The processing circuit of claim 14 , wherein when the image sensor apparatus operated under the global shutter mode and the bias transistor is turned on and become conductive, the bias transistor is used to clear or reset a voltage level in the stacked pixel level connection channel; and, when the image sensor apparatus operated under the global shutter mode and the bias transistor is turned off, at least one charge signal at the first floating diffusion node is transmitted via the stacked pixel level connection channel to the second floating diffusion node.

16. The image sensor apparatus of claim 1 , wherein the second terminal of the specific row select transistor is disconnected from the bias transistor of the processing circuit.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 24, 2021
From: TANG, KUAN; CHIU, YI-CHENG; CHIU, JUI-TE
To: PIXART IMAGING INC.
Reel/Frame 055379/0133 →
Continuity (2)
Continuation In Part 17002755 · Aug 25, 2020
Related Publication 20220070395A1 · Mar 3, 2022
Cited By (1)
US 12,513,430