Semiconductor memory device

1. A semiconductor memory device comprising:

a memory cell array; and

a control circuit configured to:

execute a write operation or erase operation on the memory cell array in response to a first command set, the first command set including a first command; and

execute a read operation on the memory cell array in response to a second command set, the second command set including the first command,

wherein the control circuit comprises:

a first data retaining circuit configured to, based on a first signal indicating timing of receiving a command or address information, retain and output a second signal based on the first command included in the first command set; and

a second data retaining circuit configured to, based on the first signal, retain and output a third signal based on the first command included in the second command set, and

wherein the execution of the write operation or erase operation is based on the second signal, and the execution of the read operation is based on the third signal.

2. The device of claim 1 , wherein:

the first data retaining circuit is further configured to receive the first signal, and

the second data retaining circuit is further configured to receive the first signal.

3. The device of claim 1 , wherein:

the first command set includes a second command, and the second command set includes a third command which differs from the second command, and

the retainment of the second signal is based on the second command, and the retainment of the third signal is based on the third command.

4. The device of claim 3 , wherein:

the control circuit further comprises a third data retaining circuit configured to retain and output a fourth signal based on the first command, and

the retainment of the second signal and the retainment of the third signal are based on the fourth signal.

5. The device of claim 4 , wherein the third data retaining circuit is further configured to erase the retained fourth signal, based on the second command or the third command.

6. The device of claim 1 , wherein the first command is a head command of the first command set and a head command of the second command set.

7. The device of claim 1 , wherein whenever the semiconductor memory device receives the first command, one of the retainment of the second signal or the retainment of the third signal is executed.

8. The device of claim 1 , wherein:

the second command set includes a second command, and

the retainment of the second signal is based on the first command set not including the second command, and the retainment of the third signal is based on the second command set including the second command.

9. The device of claim 8 , wherein:

the control circuit further comprises a third data retaining circuit configured to retain and output a fourth signal based on the second command, and

the retainment of the second signal is based on the third data retaining circuit not outputting the fourth signal, and the retainment of the third signal is based on the fourth signal.

10. The device of claim 8 , wherein the second command is a head command in the second command set.

11. The device of claim 10 , wherein:

the first command is a command subsequent to the second command in the second command set, and

the first command is a head command in the first command set.

12. The device of claim 1 , wherein:

the first command set includes a second command, and

the retainment of the second signal is based on the first command set including the second command, and the retainment of the third signal is based on the second command set not including the second command.

13. The device of claim 12 , wherein:

the control circuit further comprises a third data retaining circuit configured to retain and output a fourth signal based on the second command, and

the retainment of the second signal is based on the fourth signal, and the retainment of the third signal is based on the third data retaining circuit not outputting the fourth signal.

14. The device of claim 12 , wherein the second command is a head command in the first command set.

15. The device of claim 14 , wherein:

the first command is a command subsequent to the second command in the first command set, and

the first command is a head command in the second command set.

16. The device of claim 1 , wherein the control circuit is further configured to start the write operation on the memory cell array in response to the first command set.

17. A semiconductor memory device comprising:

a memory cell array; and

a control circuit configured to:

execute a write operation or erase operation on the memory cell array in response to a first command set, the first command set including a first command; and

execute a read operation on the memory cell array in response to a second command set, the second command set including a second command which differs from the first command,

wherein the control circuit comprises:

a first data retaining circuit configured to retain and output a first signal based on the first command,

a second data retaining circuit configured to retain and output a second signal based on the second command,

wherein the execution of the write operation or erase operation is based on the first signal, and the execution of the read operation is based on the second signal,

wherein the first command designates a mode in which the semiconductor memory device executes the write operation or erase operation, and the second command designates a mode in which the semiconductor memory device executes the read operation, and

wherein the mode designated by the first command is identical to the mode designated by the second command.

18. The device of claim 17 , wherein:

the first command is a head command of the first command set, and

the second command is a head command of the second command set.