ANALOG COUNTER CIRCUITS AND READ-OUT INTEGRATED CIRCUITS AND INFRARED DETECTORS INCORPORATING THE SAME
Analog counter circuits, read-out integrated circuits, and infrared detector devices are disclosed. In one embodiment, an analog counter circuit includes a first capacitor including a first terminal and a second terminal, a switch electrically coupled the first capacitor and a first voltage input, a field effect transistor, and a second capacitor. Setting the switch to an on-state pre-charges the first capacitor such that a voltage at the second terminal of the first capacitor is the first voltage. Applying a charge voltage at a charge input further charges the first capacitor. When a voltage at the second terminal of the first capacitor is greater than a threshold voltage of the field effect transistor, the field effect transistor turns on and transfers a charge on the first capacitor to the second capacitor.
1 . An analog counter circuit comprising:
a first capacitor comprising a first terminal electrically coupled to a charge input;
a switch electrically coupled to a second terminal of the first capacitor and a first voltage input;
a field effect transistor, wherein a source terminal of the field effect transistor is electrically coupled to a second terminal of the first capacitor and a gate terminal is electrically coupled to a gate voltage input; and
a second capacitor comprising a first terminal electrically coupled to ground and a second terminal electrically coupled to a drain terminal of the field effect transistor and a count output, wherein:
the gate voltage input has a gate voltage that is higher than a first voltage at the first voltage input,
setting the switch to an on-state pre-charges the first capacitor such that a voltage at the second terminal of the first capacitor is the first voltage,
applying a charge voltage at the charge input further charges the first capacitor, and
when a voltage at the second terminal of the first capacitor is greater than a threshold voltage of the field effect transistor, the field effect transistor turns on and transfers a charge on the first capacitor to the second capacitor, thereby accumulating voltage on the second capacitor.
2 . The analog counter circuit of claim 1 , wherein the voltage at the count output corresponds to a number of times the switch is set to the on-state and the charge voltage is applied to the second terminal of the first capacitor.
3 . The analog counter circuit of claim 1 , wherein the field effect transistor comprises a positive metal-oxide-semiconductor field-effect transistor.
4 . The analog counter circuit of claim 1 , further comprising a buffer between the charge input and the first terminal of the first capacitor.
5 . The analog counter circuit of claim 1 , further comprising a reset switch electrically coupled to the count output and ground, wherein when the reset switch is in an on-state, the second capacitor is discharged to reset a count provided by a voltage on the second capacitor.
6 . The analog counter circuit of claim 1 , wherein the first capacitor is a parasitic capacitor.
7 . The analog counter circuit of claim 1 , wherein the switch is set to an off-state to cause the voltage at the second terminal of the first capacitor to float prior to applicant the charge voltage at the charge input.
8 . The analog counter circuit of claim 1 , wherein the analog counter circuit supports at least a 7-bit dynamic range.
9 . The analog counter circuit of claim 1 , wherein the analog counter circuit is sized such that it is capable of being incorporated within a pixel of a pixel array having a pixel pitch of greater than or equal to 12 μm.
10 . A read-out integrated circuit comprising:
an array of pixels, each pixel comprising an analog counter circuit, wherein the analog counter circuit comprises:
a first capacitor comprising a first terminal electrically coupled to a charge input;
a switch electrically coupled to a second terminal of the first capacitor and a first voltage input;
a field effect transistor, wherein a source terminal of the field effect transistor is electrically coupled to a second terminal of the first capacitor and a gate terminal is electrically coupled to a gate voltage input; and
a second capacitor comprising a first terminal electrically coupled to ground and a second terminal electrically coupled to a drain terminal of the field effect transistor and a count output,
wherein:
the gate voltage input has a gate voltage that is higher than a first voltage at the first voltage input,
setting the switch to an on-state pre-charges the first capacitor such that a voltage at the second terminal of the first capacitor is the first voltage,
applying a charge voltage at the charge input further charges the first capacitor, and
when a voltage at the second terminal of the first capacitor is greater than a threshold voltage of the field effect transistor, the field effect transistor turns on and transfers a charge on the first capacitor to the second capacitor, thereby accumulating voltage on the second capacitor.
11 . The read-out integrated circuit of claim 10 , wherein the voltage at the count output corresponds to a number of times the switch is set to the on-state and the charge voltage is applied to the second terminal of the first capacitor.
12 . The read-out integrated circuit of claim 10 , wherein the field effect transistor comprises a positive metal-oxide-semiconductor field-effect transistor.
13 . The read-out integrated circuit of claim 10 , further comprising a buffer between the charge input and the first terminal of the first capacitor.
14 . The read-out integrated circuit of claim 10 , further comprising a reset switch electrically coupled to the count output and ground, wherein when the reset switch is in an on-state, the second capacitor is discharged to reset a count provided by a voltage on the second capacitor.
15 . The read-out integrated circuit of claim 10 , wherein the first capacitor is a parasitic capacitor.
16 . The read-out integrated circuit of claim 10 , wherein the switch is set to an off-state to cause the voltage at the second terminal of the first capacitor to float prior to applicant the charge voltage at the charge input.
17 . The read-out integrated circuit of claim 10 , wherein the analog counter circuit supports at least a 7-bit dynamic range.
18 . The read-out integrated circuit of claim 10 , wherein a pixel pitch of the array of pixels is greater than or equal to 12 μm.
19 . An infrared detector comprising:
a focal plane array comprising an array of infrared detector devices;
a read-out integrated circuit comprising an array of pixels electrically coupled to the array of infrared detector devices, each pixel comprising an analog counter circuit, wherein the analog counter circuit comprises:
a first capacitor comprising a first terminal electrically coupled to a charge input;
a switch electrically coupled to a second terminal of the first capacitor and a first voltage input;
a field effect transistor, wherein a source terminal of the field effect transistor is electrically coupled to a second terminal of the first capacitor and a gate terminal is electrically coupled to a gate voltage input; and
a second capacitor comprising a first terminal electrically coupled to ground and a second terminal electrically coupled to a drain terminal of the field effect transistor and a count output,
wherein:
the gate voltage input has a gate voltage that is higher than a first voltage at the first voltage input,
setting the switch to an on-state pre-charges the first capacitor such that a voltage at the second terminal of the first capacitor is the first voltage,
applying a charge voltage at the charge input further charges the first capacitor, and
when a voltage at the second terminal of the first capacitor is greater than a threshold voltage of the field effect transistor, the field effect transistor turns on and transfers a charge on the first capacitor to the second capacitor, thereby accumulating voltage on the second capacitor.
20 . The infrared detector of claim 19 , wherein the analog counter circuit supports at least a 7-bit dynamic range, and a pixel pitch of the array of pixels is greater than or equal to 12 μm.