Pre-emphasis buffer systems and related methods
Implementations of a pre-emphasis signal processing system may include an output driver which may include a pre-emphasis transistor coupled with a steady state transistor, where gates of the pre-emphasis transistor and steady state transistor may be coupled together. The system may include a regulator voltage input coupled to a source of the pre-emphasis transistor; a first resistor coupled between a drain of the pre-emphasis transistor and an output of the output driver; and a second resistor coupled between the drain of the steady state transistor and the output of the output driver; and a pre-emphasis source including a current source coupled to a delay transistor, the delay transistor coupled with the output of the output driver.
1 . A pre-emphasis signal processing system comprising:
an output driver comprising:
a pre-emphasis transistor coupled with a steady state transistor, where gates of the pre-emphasis transistor and steady state transistor are coupled together;
a regulator voltage input coupled to a source of the pre-emphasis transistor;
a first resistor coupled between a drain of the pre-emphasis transistor and an output of the output driver; and
a second resistor coupled between a drain of the steady state transistor and the output of the output driver; and
a pre-emphasis source comprising a current source coupled to a delay transistor, the delay transistor coupled with the output of the output driver.
2 . The system of claim 1 , wherein the delay transistor is a first delay buffer chain delay transistor.
3 . The system of claim 2 , further comprising a second delay buffer chain delay transistor.
4 . The system of claim 1 wherein the output of the output driver is configured to be coupled to a signal input of a universal serial bus 2.0 device.
5 . The system of claim 1 , wherein the pre-emphasis transistor and the steady state transistor are coupled in parallel with the output of the output driver.
6 . The system of claim 1 , further comprising an output of a buffer chain coupled to a signal input of the output driver.
7 . The system of claim 6 , wherein a signal input of the buffer chain is configured to couple with an embedded universal serial bus device.
8 . A pre-emphasis signal processing system comprising:
a first output driver comprising:
a first pre-emphasis transistor coupled with a first steady state transistor, where gates of the first pre-emphasis transistor and the first steady state transistor are coupled together;
a regulator voltage input coupled to a source of the first pre-emphasis transistor; and
a first signal input coupled with a first buffer chain configured to be coupled to a negative terminal of an input device; and
a first pre-emphasis source comprising a pre-emphasis current source coupled to a first delay transistor, the first delay transistor coupled with an output of the first output driver;
a second output driver comprising:
a second pre-emphasis transistor coupled with a second steady state transistor, where gates of the second pre-emphasis transistor and the second steady state transistor are coupled together;
the regulator voltage input coupled to a source of the second pre-emphasis transistor; and
a second signal input coupled with a second buffer chain configured to be coupled to a positive terminal of the input device; and
a second pre-emphasis source comprising the pre-emphasis current source coupled to a second delay transistor, the second delay transistor coupled with an output of the second output driver.
9 . The system of claim 8 , further comprising:
a first resistor coupled between a drain of the first pre-emphasis transistor and the output of the first output driver;
a second resistor coupled between a drain of the first steady state transistor and the output of the first output driver;
a third resistor coupled between the drain of the second pre-emphasis transistor and the output of the second output driver; and
a fourth resistor coupled between the drain of the second steady state transistor and the output of the second output driver.
10 . The system of claim 8 , wherein the first delay transistor and the second delay transistor are first delay buffer chain delay transistors.
11 . The system of claim 10 , further comprising a third delay buffer chain delay transistor and a fourth delay buffer chain delay transistor.
12 . The system of claim 8 , wherein the output of the first output driver and the output of the second output driver are configured to be coupled to a positive signal input and to a negative signal input, respectively, of a universal serial bus 2.0 device.
13 . The system of claim 8 , wherein the first pre-emphasis transistor and the second pre-emphasis transistor are both PMOS transistors and the first steady state transistor and the second steady state transistor are both NMOS transistors.
14 . The system of claim 8 , further comprising an output of a first buffer chain coupled to a signal input of the first output driver and an output of a second buffer chain coupled to a signal input of the second output driver.
15 . The system of claim 14 , wherein a signal input of the first buffer chain is configured to couple with a negative terminal of an embedded universal serial bus device and a signal input of the second buffer chain is configured to couple with a positive terminal of the embedded universal serial bus device.
16 . A method of pre-emphasis signal processing, the method comprising:
generating rising pre-emphasis in a voltage signal by:
using a first output driver, turning on a first pre-emphasis transistor, a regulator voltage input coupled with a source of the first pre-emphasis transistor; and
using a first pre-emphasis source, turning on a first delay transistor coupled to a first pre-emphasis current source and to an output of the first output driver;
increasing an initial voltage of an input signal received by the first output driver using the first pre-emphasis current source and a resistor coupled between a drain of the first pre-emphasis transistor and an output of the first output driver; and
generating falling pre-emphasis in the voltage signal by:
using a second output driver, turning on a steady state transistor; and
using a second pre-emphasis source, turning off a second delay transistor coupled to the first pre-emphasis current source and with an output of the second output driver; and
decreasing an initial voltage of the input signal received by the second output driver using the first pre-emphasis current source and a resistor coupled between a drain of a second pre-emphasis transistor and an output of the second output driver.
17 . The method of claim 16 , wherein the output of the first output driver and the output of the second output driver are configured to be coupled to a positive signal input and to a negative signal input, respectively, of a universal serial bus 2.0 device.
18 . The method of claim 16 , further comprising:
buffering data using a first buffer chain coupled to a signal input of the first output driver; and
buffering data using a second buffer chain coupled to a signal input of the second output driver.
19 . The method of claim 18 , further comprising:
delaying data for a period of a unit interval of a data rate using a first delay buffer chain coupled to a signal input of the first output driver;
delaying data for the period of the unit interval of the data rate using a second delay buffer chain coupled to a signal input of the second output driver; and
using the first delay buffer chain and the second delay buffer chain, timing the rising pre-emphasis and the falling pre-emphasis in the voltage signal.
20 . The method of claim 18 , wherein a signal input of the first buffer chain is configured to couple with a negative terminal of an embedded universal serial bus device and a signal input of the second buffer chain is configured to couple with a positive terminal of the embedded universal serial bus device.