Semiconductor storage device
A semiconductor storage device includes memory strings, bit lines connected to the memory strings, respectively, sense transistors of which gates are connected to the bit lines, respectively, first transistors connected between the bit lines and the gates of the sense transistors, respectively, and a control circuit. Each of the memory strings includes first and second memory transistors adjacent to each other. The control circuit is configured to perform, during a first write sequence, a read operation with respect to the second memory transistors, a program operation with respect to the first memory transistors, and a verify operation with respect to the first memory transistors, in this order. During the verify operation, the control circuit turns on the first transistors during a first sense period, and then turns on the first transistors during a second sense period longer than the first sense period.
1. A semiconductor storage device, comprising:
a plurality of memory strings, each including first and second memory transistors adjacent to each other;
a plurality of bit lines connected to the memory strings, respectively;
a plurality of sense transistors having gates connected to the bit lines, respectively;
a plurality of first transistors connected between the bit lines and the gates of the sense transistors, respectively; and
a control circuit configured to perform, during a first write sequence, a read operation with respect to the second memory transistors of the memory strings, a program operation with respect to the first memory transistors of the memory strings, and a verify operation with respect to the first memory transistors of the memory strings, in this order, wherein
during the read operation, the control circuit determines a first part of the second memory transistors having a threshold voltage higher than a predetermined value and a second part of the second memory transistors not having a threshold voltage higher than the predetermined value, and
during the verify operation, the control circuit turns on the first transistors during a first sense period while one or more of the bit lines connected to the first part are at a first voltage and one or more of the bit lines connected to the second part are at a second voltage lower than the first voltage, and then turns on the first transistors during a second sense period longer than the first sense period while the one or more of the bit lines connected to the first part are at the second voltage and the one or more of the bit lines connected to the second part are at the first voltage.
2. The semiconductor storage device according to claim 1 , wherein
during the read operation, the control circuit determines a third part of the second memory transistors having a threshold voltage higher than a second predetermined value different from the predetermined value and a fourth part of the second memory transistors not having a threshold voltage higher than the second predetermined value, and
during the verify operation, the control circuit turns on the first transistors during a third sense period while one or more of the bit lines connected to the third part are at the first voltage and one or more of the bit lines connected to the fourth part are at the second voltage, and then turns on the first transistors during a fourth sense period longer than the third sense period while the one or more of the bit lines connected to the third part are at the second voltage and the one or more of the bit lines connected to the fourth part are at the first voltage.
3. The semiconductor storage device according to claim 2 , wherein
the semiconductor storage device stores values of a plurality of verify voltages, and
the control circuit controls gates of the first memory transistors to be at a first one of the stored verify voltages during the first and second sense periods, and at a second one of the verify voltages different from the first one during the third and fourth sense periods.
4. The semiconductor storage device according to claim 3 , wherein during the read operation, the control circuit controls the gates of the second memory transistors to be at a third one of the stored verify voltages.
5. The semiconductor storage device according to claim 4 , wherein the third one of the stored verify voltages is equal to the first one or the second one of the stored verify voltages.
6. The semiconductor storage device according to claim 4 , wherein during the read operation, the control circuit controls the gates of the second memory transistors to be at a fourth one of the stored verify voltages different from the third one.
7. The semiconductor storage device according to claim 1 , wherein the control circuit is configured to alternately repeat the program operation and the verify operation after the read operation during the first write sequence.
8. The semiconductor storage device according to claim 1 , wherein the control circuit is configured to perform an erase operation and then a second write sequence with respect to the first memory transistors of the memory strings, and perform the first write sequence after the second write sequence.
9. The semiconductor storage device according to claim 8 , wherein during the second write sequence, no read operation with respect to the second memory transistors of the memory strings is performed.
10. The semiconductor storage device according to claim 8 , wherein the control circuit is configured to perform a third write sequence with respect to the second memory transistors of the memory strings after the second write sequence and before the first write sequence.
11. The semiconductor storage device according to claim 10 , wherein during the third write sequence, no read operation with respect to the second memory transistors of the memory strings is performed.
12. A semiconductor storage device, comprising:
a memory string including first and second memory transistors adjacent to each other;
a first wiring connected to a gate of the first memory transistor;
a second wiring connected to a gate of the second memory transistor; and
a control circuit configured to perform, during a first write sequence, a read operation with respect to the second memory transistor, a program operation with respect to the first memory transistor, and a verify operation with respect to the first memory transistor, in this order, wherein
during the read operation, the control circuit controls the first wiring to be at a read pass voltage and the second wiring to be at a read voltage less than the read pass voltage,
during the program operation, the control circuit controls the first wiring to be at a program voltage greater than the read pass voltage and the second wiring to be at a write pass voltage less than the program voltage and greater than the read voltage, and
during the verify operation, the control circuit controls the first wiring to be at a verify voltage less than the read pass voltage and the second wiring to be at the read pass voltage.
13. The semiconductor storage device according to claim 12 , wherein the write pass voltage is greater than the read pass voltage.
14. The semiconductor storage device according to claim 12 , wherein
the semiconductor storage device stores values of a plurality of verify voltages, including the verify voltage, and
the read voltage is equal to one of the verify voltages.
15. The semiconductor storage device according to claim 12 , wherein
during a first time period in the verify operation, the control circuit controls the first wiring to be at a first verify voltage less than the read pass voltage and the second wiring to be at the read pass voltage, and
during a second time period in the verify operation, the control circuit controls the first wiring to be at a second verify voltage less than the read pass voltage and the second wiring to be at the read pass voltage, the second verify voltage being different from the first verify voltage.
16. The semiconductor storage device according to claim 12 , wherein the control circuit is configured to alternately repeat the program operation and the verify operation after the read operation during the first write sequence.
17. The semiconductor storage device according to claim 12 , wherein the control circuit is configured to perform an erase operation and then a second write sequence with respect to the first memory transistor, and perform the first write sequence after the second write sequence.
18. The semiconductor storage device according to claim 17 , wherein during the second write sequence, no read operation with respect to the second memory transistor is performed.
19. The semiconductor storage device according to claim 17 , wherein the control circuit is configured to perform a third write sequence with respect to the second memory transistor after the second write sequence and before the first write sequence.
20. The semiconductor storage device according to claim 19 , wherein during the third write sequence, no read operation with respect to the second memory transistor is performed.