IP Library › Granted Patent US 12,364,172
Granted Patent B2
US 12,364,172 · App. 17/189,173 · Granted Jul 15, 2025

Electrical memristive devices based on bilayer arrangements of HfO

Inventors: Bert Jan Offrein (Schoenenberg, CH); Valeria Bragaglia (Thalwil, CH); Folkert Horst (Wettingen, CH); Antonio La Porta (Kilchberg, CH); Roger F. Dangel (Zug, CH); Daniel S. Jubin (Langnau am Albis, CH)
Assignee: International Business Machines Corporation
H10N70/841G06N3/065H10B63/84H10N70/023H10N70/8833
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Quick Facts
Patent No.
US 12,364,172
App. No.
17/189,173
Granted
Jul 15, 2025
Kind
B2
Abstract

An electrical memristive device has a layer structure. The layer structure comprises two electrodes and a bilayer material arrangement that connects the two electrodes. The bilayer material arrangement may, for example, be sandwiched by the two electrodes, in direct contact therewith. The bilayer material arrangement includes an HfO y layer, where 1.3±0.1≤y<1.9±0.1, as well as a WO x layer in direct contact with the HfO y layer, where 2.5±0.1≤x<2.9±0.1. The bilayer arrangement involves sub-stoichiometric layers of HfO y and WO x , where the WO x layer may advantageously have a polycrystalline structure in the monoclinic phase, while the HfO y layer is preferably amorphous.

Claims (66)

1. An electrical memristive device having a layer structure comprising:

two electrodes, and,

connecting the two electrodes, a bilayer material arrangement including:

an HfO y layer, wherein 1.3±0.1≤y<1.9±0.1; and

a WO x layer in direct contact with the HfO y layer, wherein 2.5±0.1≤x<2.9±0.1, and wherein the WO x layer has a polycrystalline structure in a monoclinic phase.

2. The electrical memristive device according to claim 1 , wherein

the HfO y layer and the WO x layer are stacked along a direction perpendicular to an average plane of the bilayer material arrangement; and

the average dimensions of grains of the WO x layer are

larger than or equal to 20 nm along said direction, and

larger than or equal to 10 nm in said average plane of the bilayer material arrangement.

3. The electrical memristive device according to claim 2 , wherein

the WO x layer has an electrical resistivity that is between 10 −2 ohm-cm and 10 2 ohm-cm.

4. The electrical memristive device according to claim 2 , wherein

the HfO y layer is amorphous.

5. The electrical memristive device according to claim 1 , wherein

each of the two electrodes comprises one or more of Pt, W, and TiN.

6. The electrical memristive device according to claim 1 , wherein

the two electrodes comprise a first electrode and a second electrode, each formed as a layer,

the first electrode is in direct contact with the HfO y layer, while second electrode is in direct contact with the WO x layer; and

the electrical memristive device further comprises:

a substrate supporting the first electrode;

an electrical contact in electrical communication with the second electrode; and

an electrically insulating layer embedding the second electrode.

7. The electrical memristive device according to claim 6 , wherein

the substrate comprises silicon;

the electrical memristive device further comprises an additional electrical contact in electrical communication with the first electrode, through a via formed in the electrically insulating layer and the HfO y layer, the additional electrical contact extending opposite to the substrate with respect to the second electrode.

8. The electrical memristive device according to claim 1 , wherein

a thickness of the WO x layer is between 10 nm and 100 nm.

9. The electrical memristive device according to claim 8 , wherein

a thickness of the HfO y layer is between 3 nm and 10 nm.

10. The electrical memristive device according to claim 9 , wherein

a thickness of one or each of the two electrodes is between 10 nm and 100 nm.

11. An apparatus comprising

a plurality of electrical memristive devices, each electrical memristive device having a layer structure comprising:

two electrodes, and,

connecting the two electrodes, a bilayer material arrangement including:

an HfO y layer, wherein 1.3±0.1≤y<1.9±0.1; and

a WO x layer in direct contact with the HfO y layer, wherein 2.5±0.1≤x<2.9±0.1, and wherein the WO x layer has a polycrystalline structure in a monoclinic phase;

an input circuit connected to the electrical memristive devices, so as to be able to operate the latter, in operation; and

a readout circuit connected to the devices, the readout circuit configured to sense electrical signals impacted by electrical conductances of the electrical memristive devices, in operation.

12. The apparatus according to claim 11 , wherein

the apparatus is configured as an artificial neural network hardware having a crossbar array structure that includes input lines and output lines, and

the input lines and the output lines of the crossbar array structure are interconnected at junctions, each including one of the electrical memristive devices, the latter configured as synaptic elements of the artificial neural network hardware.

13. A method of fabricating an electrical memristive device, the method comprising

providing a substrate; and

obtaining

a first electrode extending on top of the substrate, in electrical contact therewith;

an HfO y layer extending on top of the first electrode, in electrical communication therewith, where 1.3±0.1≤y<1.9±0.1;

a WO x layer in direct contact with the HfO y layer, where 2.5±0.1≤x<2.9±0.1, and where the WO x layer has a polycrystalline structure in a monoclinic phase; and

a second electrode extending on top of the WO x layer, so as for the second electrode to be in electrical communication with the WO x layer.

14. The method according to claim 13 , wherein

each of the first electrode layer and the HfO y layer is obtained by atomic layer deposition, the HfO y layer being deposited subsequently to the first electrode layer, without exposing the first electrode layer to air.

15. The method according to claim 14 , wherein the WO x layer is obtained by

sputtering tungsten in vacuum to obtain a layer of tungsten;

oxidizing the layer of tungsten at a temperature between 300 C and 450 C to obtain a WO 3 layer; and

reducing the WO 3 layer obtained to obtain the WO x layer.

16. The method according to claim 15 , wherein

the layer of tungsten deposited has a thickness of 7 nm; and

the temperature and the duration for oxidizing the layer of tungsten are chosen so as to obtain a WO 3 layer having a thickness of 23 nm.

17. The method according to claim 16 , wherein

said temperature is a temperature of crystallization of WO 3 in the WO 3 layer.

18. The method according to claim 13 , wherein

the second electrode is obtained as a TiN electrode by sputtering.

19. The method according to claim 18 , wherein the method further comprises:

cladding the TiN electrode with SiO 2 ; and

obtaining a tungsten electrical contact in direct contact with the TiN electrode by sputter deposition.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 1, 2021
From: OFFREIN, BERT JAN; BRAGAGLIA, VALERIA; HORST, FOLKERT; LA PORTA, ANTONIO; DANGEL, ROGER F.; JUBIN, DANIEL S.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 055450/0204 →
Continuity (1)
Related Publication 20220278274A1 · Sep 1, 2022
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