Semiconductor device and method
In an embodiment, a device includes: a first channel region; a second channel region; and a gate structure around the first channel region and the second channel region, the gate structure including: a gate dielectric layer; a first p-type work function metal on the gate dielectric layer, the first p-type work function metal including fluorine and aluminum; a second p-type work function metal on the first p-type work function metal, the second p-type work function metal having a lower concentration of fluorine and a lower concentration of aluminum than the first p-type work function metal; and a fill layer on the second p-type work function metal.
1. A device comprising:
a first channel region;
a second channel region; and
a gate structure around the first channel region and the second channel region, the gate structure comprising:
a gate dielectric layer;
a first p-type work function metal on the gate dielectric layer, the first p-type work function metal comprising fluorine and aluminum;
a second p-type work function metal on the first p-type work function metal, the second p-type work function metal having a lower concentration of fluorine and a lower concentration of aluminum than the first p-type work function metal; and
a fill layer on the second p-type work function metal.
2. The device of claim 1 , wherein a first region of the gate structure is disposed between the first channel region and the second channel region, and wherein a ratio of fluorine to aluminum in the first region of the gate structure is in a range of 0.005 to 0.1.
3. The device of claim 1 , wherein the gate structure further comprises:
metal residue at an interface between the first p-type work function metal and the second p-type work function metal, the metal residue comprising aluminum and tungsten.
4. The device of claim 3 , wherein a first region of the gate structure is disposed between the first channel region and the second channel region, and wherein a ratio of fluorine to tungsten in the first region of the gate structure is in a range of 0.005 to 0.1.
5. The device of claim 1 , wherein the gate dielectric layer comprises fluorine and hafnium.
6. The device of claim 5 , wherein a first region of the gate structure is disposed between the first channel region and the second channel region, and wherein a ratio of fluorine to hafnium in the first region of the gate structure is in a range of 0.015 to 0.2.
7. A device comprising:
a channel region;
an interfacial layer on the channel region;
a high-k gate dielectric layer on the interfacial layer;
a first work function tuning layer on the high-k gate dielectric layer, the first work function tuning layer comprising a first p-type work function metal, aluminum in the first p-type work function metal, and fluorine in the first p-type work function metal;
a second work function tuning layer on the first work function tuning layer, the second work function tuning layer comprising a second p-type work function metal, the second work function tuning layer free from fluorine and aluminum;
an adhesion layer on the second work function tuning layer; and
a fill layer on the adhesion layer.
8. The device of claim 7 , wherein the high-k gate dielectric layer comprises fluorine and hafnium, the high-k gate dielectric layer is free from aluminum.
9. The device of claim 7 , wherein the first work function tuning layer and the second work function tuning layer are titanium nitride.
10. The device of claim 7 , wherein the first work function tuning layer is titanium nitride and the second work function tuning layer is tantalum nitride.
11. A method comprising:
depositing a gate dielectric layer on a channel region;
depositing a first p-type work function metal on the gate dielectric layer;
performing an aluminum treatment on the first p-type work function metal;
after performing the aluminum treatment, performing a fluorine treatment on the first p-type work function metal; and
after performing the fluorine treatment, depositing a second p-type work function metal on the first p-type work function metal.
12. The method of claim 11 , wherein the aluminum treatment incorporates aluminum into the first p-type work function metal, wherein the fluorine treatment incorporates fluorine into the first p-type work function metal, wherein the fluorine incorporated during the fluorine treatment bonds to the aluminum incorporated during the aluminum treatment.
13. The method of claim 11 , wherein the aluminum treatment is a first deposition process that exposes a surface of the first p-type work function metal to an aluminum-containing precursor, and wherein the fluorine treatment is a second deposition process that exposes the surface of the first p-type work function metal to a fluorine-containing precursor.
14. The method of claim 13 , wherein the fluorine-containing precursor is WF x , NF x , TiF x , TaF x , or HfF x , and wherein x is an integer in a range of 1 to 6.
15. The method of claim 13 , wherein the aluminum-containing precursor is triethylaluminium or trimethylaluminium.
16. The method of claim 13 , wherein the first deposition process and the second deposition process are performed in a same deposition chamber.
17. The method of claim 13 , wherein the first deposition process and the second deposition process are performed at a same temperature.
18. The method of claim 13 , wherein the first deposition process and the second deposition process are performed at different temperatures.
19. The method of claim 11 , wherein no aluminum diffuses into the gate dielectric layer during the aluminum treatment.
20. The method of claim 11 , wherein fluorine diffuses into the gate dielectric layer during the fluorine treatment.