Semiconductor device
According to one embodiment, a semiconductor device includes a first chip, and a second chip bonded to the first chip. The first chip includes: a substrate; a transistor provided on the substrate; a plurality of first wirings provided above the transistor; and a plurality of first pads provided above the first wirings. The second chip includes: a plurality of second pads coupled to the plurality of first pads, respectively; a plurality of second wirings provided above the second pads; and a memory cell array provided above the second wirings. The first wiring, the first pad, the second pad, and the second wiring are coupled to one another in series to form a first pattern.
1. A semiconductor device comprising:
a first chip; and
a second chip bonded to the first chip in a first direction, wherein
the first chip includes:
a substrate;
a transistor provided on the substrate;
a plurality of first wirings provided above the transistor and extending in a second direction crossing the first direction; and
a plurality of first pads provided above the first wirings, the second chip includes:
a plurality of second pads coupled to the plurality of first pads, respectively;
a plurality of second wirings provided above the second pads and extending in the second direction; and
a memory cell array provided above the second wirings;
a third pad connected to at least one of the first wirings; and
a fourth pad connected to at least one of the second wirings,
wherein a length of the at least one first wiring extending from the third pad to a first or last of either the first or second pads is equal to or less than 1 mm in the second direction;
wherein a length of the at least one second wirings extending from the fourth pad to the first or last of either the first or second pads is equal to or less than 1 mm, and
wherein the first wiring, the first pad, the second pad, and the second wiring form a first pattern, the first pattern having the following order of connections: the first wiring, the first pad, the second pad, and the second wiring connected to each other in series.
2. The semiconductor device according to claim 1 , wherein the first pattern overlaps with the memory cell array, when viewed from the top.
3. The semiconductor device according to claim 1 , wherein the first pattern overlaps with both of the memory cell array and a stepped structure portion provided at an end of the memory cell array, when viewed from the top.
4. The semiconductor device according to claim 1 , wherein the first pattern overlaps with all of the memory cell array, a stepped structure portion provided at an end of the memory cell array, and a test pattern region around the stepped structure portion, when viewed from the top.
5. The semiconductor device according to claim 1 , further comprising one or more test chain patterns configured to test connections between the first pads and second pads.
6. The semiconductor device according to claim 5 , wherein the one or more test chain patterns are not connected with the memory cell array.