Electroless plating method for metal gate fill

1. A method comprising:

etching a dummy gate of a transistor to remove the dummy gate and form a first opening;

etching to remove first nanostructures and to extend the first opening, thereby exposing second nanostructures of the transistor;

depositing a first dielectric layer in the first opening, the first dielectric layer surrounding the second nanostructures;

depositing a first work function layer in the first opening, the first work function layer surrounding the second nanostructures and the first dielectric layer;

depositing a glue layer in the first opening, the glue layer surrounding the second nanostructures; and

submerging the first opening in an electro-chemical plating solution to plate a metal into the first opening, the metal filling the first opening, the electro-chemical plating solution comprising accelerators, wherein the accelerators are more densely distributed at a bottom of the first opening than at sidewalls of the first opening during plating the metal.

2. The method of claim 1 , wherein the electro-chemical plating solution further comprises metal ions or metal salts, a reducer, and suppressors.

3. The method of claim 2 , wherein the suppressors are more densely distributed at the sidewalls of the first opening than at the bottom of the first opening during plating the metal.

4. The method of claim 1 , further comprising:

planarizing the metal filling, the glue layer, the first work function layer, and the first dielectric layer to level upper surfaces of the metal filling, the glue layer, the first work function layer, and the first dielectric layer with each other.

5. The method of claim 1 , further comprising:

prior to depositing the first dielectric layer in the first opening, depositing an interfacial layer in the first opening, the interfacial layer surrounding the second nanostructures.

6. The method of claim 1 , wherein plating the metal comprises:

depositing the metal using a bottom up process.

7. The method of claim 1 , wherein plating the metal comprises:

filling a space vertically between the second nanostructures.

8. The method of claim 1 , wherein the first work function layer around a first one of the second nanostructures merges with the first work function layer around a second one of the second nanostructures.

9. A method comprising:

growing epitaxial source/drain regions in a fin recess on either side of a gate;

performing a replacement gate process, the replacement gate process comprising:

removing a dummy gate structure between two gate spacers of the gate to form an opening between the two gate spacers;

depositing a first gate dielectric layer in the opening, the first gate dielectric layer covering a channel region of the gate;

depositing a work function layer in the opening, the work function layer covering the first gate dielectric layer; and

plating a conductive fill in the opening by an electroless plating process, the electroless plating process plating the conductive fill at a bottom of the opening at a plating rate which is 10 to 25 times greater than at sides of the opening.

10. The method of claim 9 , wherein the plating comprises:

submerging the opening in a plating solution, the plating solution comprising a metal ion and a reducing agent.

11. The method of claim 10 , wherein the plating solution further comprises accelerators and suppressors, a ratio of accelerators to suppressors being between 10:1 and 100:1 at the bottom of the opening.

12. The method of claim 11 , wherein an overall ratio of accelerators to suppressors by weight in the plating solution is between 1:5 and 5:1.

13. The method of claim 9 , further comprising:

planarizing the gate to level upper surfaces of the first gate dielectric layer, work function layer, and conductive fill to each other.

14. The method of claim 9 , wherein the work function layer fills a space between two nanostructures of the channel region.

15. A method comprising:

forming a first nano field effect transistor (nano-FET) gate structure, the forming comprising:

forming multiple nanostructure channel regions,

depositing a gate dielectric layer surrounding the multiple nanostructure channel regions,

depositing a gate work function layer surrounding the gate dielectric layer, and

depositing a gate fill surrounding the gate work function layer, the depositing the gate fill comprising:

providing a plating solution in an opening corresponding to the gate fill,

providing accelerators and suppressors in the plating solution, and

reducing a metal from the plating solution to deposit the metal at a bottom of the opening; and

forming a first epitaxial source/drain region and a second epitaxial source/drain region disposed on either side of the first nano-FET gate structure, wherein the multiple nanostructure channel regions extend from the first epitaxial source/drain region to the second epitaxial source/drain region, wherein a height to width ratio of the gate fill is between 10:1 and 20:1 in a cross-section through the first epitaxial source/drain region and the second epitaxial source/drain region.

16. The method of claim 15 , wherein the gate fill comprises an oxidation of the suppressors or an oxidation of the accelerators, and wherein the gate fill is free of fluorine.

17. The method of claim 15 , wherein the gate fill comprises an oxide of the metal or a byproduct of a reducing agent.

18. The method of claim 15 , wherein the metal comprises tungsten, cobalt, or nickel.

19. The method of claim 15 wherein the gate work function layer comprises a p-metal work function tuning layer.

20. The method of claim 15 , wherein a ratio of the accelerators to the suppressors is between 10:1 and 100:1 at the bottom of the opening while depositing the gate fill.