Semiconductor structure and method of forming the same

1. A semiconductor structure, comprising:

a substrate including a well region and an adjustment region over the well region;

an isolation structure disposed over the substrate and at least partially surrounding the well region and the adjustment region;

an epitaxial layer disposed over the adjustment region and surrounded by the isolation structure; and

a gate structure disposed on the epitaxial layer, wherein the gate structure includes a gate spacer contacting the epitaxial layer.

2. The semiconductor structure of claim 1 , wherein the gate structure includes a gate dielectric on the epitaxial layer, a gate conductor on the gate dielectric and the gate spacer surrounds the gate dielectric and the gate conductor.

3. The semiconductor structure of claim 2 , wherein the epitaxial layer has a thickness of about 15 to about 60 angstroms (Å) and the thickness of the epitaxial layer is substantially greater than a thickness of the gate dielectric.

4. The semiconductor structure of claim 1 , wherein the epitaxial layer includes dopant-free silicon.

5. The semiconductor structure of claim 1 , wherein the well region and the adjustment region include impurity atoms.

6. The semiconductor structure of claim 1 , wherein the epitaxial layer is in direct contact with the gate dielectric.

7. A semiconductor structure, comprising:

a substrate including a bulk region and a well region disposed over the bulk region;

an isolation structure disposed over the bulk region and at least partially surrounding the well region;

an epitaxial layer disposed over the well region and surrounded by the isolation structure; and

a gate structure disposed on the epitaxial layer, wherein the gate structure includes a gate spacer contacting the epitaxial layer.

8. The semiconductor structure of claim 7 , wherein the gate structure includes a gate dielectric over the epitaxial layer.

9. The semiconductor structure of claim 7 , wherein a portion of the epitaxial layer beneath the gate structure has substantially same concentration of impurity atoms as the bulk region.

10. The semiconductor structure of claim 7 , wherein the bulk region and the epitaxial layer are free of impurity atom, and the well region includes impurity atoms.

11. The semiconductor structure of claim 7 , further comprising a source/drain region disposed in portions of the epitaxial layer and at opposite sides of the gate structure.

12. The semiconductor structure of claim 11 , wherein a portion of the epitaxial layer surrounded by the source/drain region includes dopant-free silicon.

13. A method for fabricating a semiconductor structure, comprising:

providing a substrate;

forming an isolation structure to surround at least a portion of the substrate;

performing a first implantation on the substrate to form a well region in the substrate;

performing a second implantation on the substrate to form an adjustment region over the well region;

growing an epitaxial layer over the adjustment region; and

forming a gate structure on the epitaxial layer, wherein the forming of the gate structure includes forming a gate spacer contacting the epitaxial layer.

14. The method of claim 13 , wherein the second implantation is performed after the first implantation.

15. The method of claim 13 , further comprising performing an annealing after the first implantation or the second implantation.

16. The method of claim 13 , wherein the growth of the epitaxial layer comprises forming dopant-free silicon over the substrate.

17. The method of claim 13 , wherein the formation of the gate structure comprises:

forming a gate dielectric over the epitaxial layer;

forming a gate conductor on the gate dielectric; and

removing portions of the gate dielectric and the gate conductor.

18. The method of claim 17 , wherein the formation of the gate dielectric includes oxidizing a portion of the epitaxial layer distal to the substrate.

19. The method of claim 17 , wherein the formation of the gate dielectric includes depositing an oxide on the epitaxial layer.

20. The method of claim 13 , wherein the gate spacer surrounds the gate dielectric and the gate conductor.