Memory cell and operating method of memory cell
A memory cell includes a first electrode, a second electrode, a variable resistance layer located between the first electrode and the second electrode, and a ferroelectric layer located between the variable resistance layer and the second electrode, wherein the variable resistance layer is maintained in an amorphous state during a program operation.
1. A memory cell, comprising:
a first electrode;
a second electrode;
a variable resistance layer located between the first electrode and the second electrode, and reversibly transitioning between different resistance states; and
a ferroelectric layer located between the variable resistance layer and the second electrode,
wherein the variable resistance layer is maintained in an amorphous state during a program operation.
2. The memory cell of claim 1 , wherein the memory cell has a first threshold voltage after a positive program operation and the memory cell has a second threshold voltage after a negative program operation, and
wherein the second threshold voltage is greater than the first threshold voltage.
3. The memory cell of claim 2 , wherein a read voltage is between the first threshold voltage and the second threshold voltage.
4. The memory cell of claim 1 , wherein the variable resistance layer has a low-resistance amorphous state after a set operation and the variable resistance layer has a high-resistance amorphous state after a reset operation.
5. The memory cell of claim 1 , wherein the variable resistance layer includes a chalcogenide.
6. The memory cell of claim 1 , wherein during a positive program operation, a positive program voltage is applied to the first electrode and causes polarization of the ferroelectric layer.
7. The memory cell of claim 1 , wherein during a negative program operation, a negative program voltage is applied to the first electrode and causes polarization of the ferroelectric layer.
8. A method of operating a memory cell including a first electrode, a second electrode, a variable resistance layer located between the first electrode and the second electrode, and a ferroelectric layer located between the variable resistance layer and the second electrode, the method comprising:
applying a positive program voltage to the first electrode, wherein the positive program voltage causes polarization of the ferroelectric layer; and
applying a read voltage that does not polarize the ferroelectric layer to the memory cell.
9. The method of claim 8 , wherein the variable resistance layer is maintained in an amorphous state after the positive program voltage is applied.
10. The method of claim 8 , wherein the variable resistance layer includes a chalcogenide.
11. The method of claim 8 , wherein a resistance of the variable resistance layer is reduced by the positive program voltage.
12. The method of claim 8 , further comprising
applying a negative program voltage to the first electrode, wherein the negative program voltage causes polarization of the ferroelectric layer.
13. The method of claim 12 , wherein a resistance of the variable resistance layer is increased by the negative program voltage.
14. A method of operating a memory cell including a first electrode, a second electrode, a switching layer located between the first electrode and the second electrode, and a ferroelectric layer located between the switching layer and the second electrode, the method comprising:
applying a positive program voltage to the first electrode, wherein the positive program voltage causes polarization of the ferroelectric layer; and
applying a read voltage that does not polarize the ferroelectric layer to the memory cell.
15. The method of claim 14 , further comprising
applying a negative program voltage to the first electrode, wherein the negative program voltage causes polarization of the ferroelectric layer.
16. The method of claim 14 , wherein the switching layer includes a chalcogenide layer and the switching layer is maintained in an amorphous state after the positive program voltage is applied.