FET with wrap-around silicide and fabrication methods thereof
The present disclosure provides a semiconductor device that includes a semiconductor fin disposed over a substrate, an isolation structure at least partially surrounding the fin, an epitaxial source/drain (S/D) feature disposed over the semiconductor fin, where an extended portion of the epitaxial S/D feature extends over the isolation structure, and a silicide layer disposed on the epitaxial S/D feature, where the silicide layer covers top, bottom, sidewall, front, and back surfaces of the extended portion of the S/D feature.
1. A semiconductor device, comprising:
a semiconductor fin disposed over a substrate;
an isolation structure at least partially surrounding the semiconductor fin;
a source/drain (S/D) feature disposed over the semiconductor fin, wherein an extended portion of the S/D feature extends over the isolation structure; and
a silicide layer disposed over the S/D feature, wherein the silicide layer fully wraps around the extended portion of the S/D feature when viewed in a cross-section cut vertically along a length of the semiconductor fin.
2. The semiconductor device of claim 1 , wherein the semiconductor device further comprises a spacer layer directly on top and bottom surfaces of the silicide layer.
3. The semiconductor device of claim 2 , wherein the semiconductor device further comprises a gate structure disposed over a channel region of the semiconductor fin and interposed with semiconductor layers of the semiconductor fin, wherein the silicide layer covers a sidewall of the S/D feature facing the gate structure.
4. The semiconductor device of claim 3 , wherein the spacer layer disposes between the silicide layer and the gate structure.
5. The semiconductor device of claim 3 , wherein a portion of the spacer layer is disposed over a sidewall of the silicide layer facing the gate structure.
6. The semiconductor device of claim 3 , wherein a portion of the spacer layer is disposed under a sidewall of the silicide layer facing the gate structure.
7. The semiconductor device of claim 3 , further comprising a dielectric fin disposed over the substrate and adjacent to the semiconductor fin, wherein the spacer layer covers a top surface of the dielectric fin.
8. A semiconductor device, comprising:
a semiconductor fin disposed in an isolation feature over a substrate;
a dielectric fin disposed over the isolation feature and adjacent to the semiconductor fin;
an epitaxial source/drain (S/D) feature wrapping around the semiconductor fin, wherein the epitaxial S/D feature is disposed in a concave of an interlayer dielectric layer;
a silicide layer wrapping around the epitaxial S/D feature; and
a spacer layer wrapping around the silicide layer, wherein a portion of the spacer layer is disposed between the isolation feature and the silicide layer.
9. The semiconductor device of claim 8 , wherein the silicide layer wraps around top, bottom, and sidewall surfaces of the epitaxial S/D feature.
10. The semiconductor device of claim 8 , wherein the spacer layer includes a top vertical portion covering the silicide layer in the concave, a lateral portion covering a top surface of the dielectric fin, and a bottom vertical portion filling in a gap between the semiconductor fin and the dielectric fin.
11. The semiconductor device of claim 8 , wherein the semiconductor device further comprises a gate structure disposed over a channel region of the semiconductor fin, wherein the gate structure interposes with semiconductor layers of the semiconductor fin, and wherein a sidewall of the silicide layer covers a sidewall of the epitaxial S/D feature facing the gate structure.
12. The semiconductor device of claim 11 , wherein the spacer layer fills in a gap between the silicide layer and the gate structure.
13. The semiconductor device of claim 11 , wherein a portion of the spacer layer is disposed over the sidewall of the silicide layer.
14. The semiconductor device of claim 11 , wherein a portion of the spacer layer is disposed under the sidewall of the silicide layer.
15. A semiconductor device, comprising:
a fin including a stack of semiconductor layers disposed over a substrate;
an epitaxial source/drain (S/D) feature wrapping around the fin;
a gate structure disposed over the substrate, wherein the gate structure includes a top portion disposed over the fin and a bottom portion interleaved with the stack of semiconductor layers;
a silicide layer wrapping around the epitaxial S/D feature, wherein a side wall of the silicide layer covers a sidewall of the epitaxial S/D feature facing the gate structure; and
an S/D contact disposed adjacent to the gate structure, wherein the S/D contact contacts the silicide layer.
16. The semiconductor device of claim 15 , wherein the semiconductor device further comprises a spacer layer between the sidewall of the silicide layer and the gate structure.
17. The semiconductor device of claim 16 , wherein a portion of the spacer layer is disposed on top of the side wall of the silicide layer.
18. The semiconductor device of claim 16 , wherein a portion of the spacer layer is disposed under the sidewall of the silicide layer.
19. The semiconductor device of claim 16 , further comprising a dielectric fin disposed over the substrate and adjacent to the fin, wherein the spacer layer covers a top surface of the dielectric fin.
20. The semiconductor device of claim 16 , wherein the spacer layer wraps around the silicide layer.