Concurrent program execution optimization
An architecture for a load-balanced groups of multi-stage manycore processors shared dynamically among a set of software applications, with capabilities for destination task defined intra-application prioritization of inter-task communications (ITC), for architecture-based ITC performance isolation between the applications, as well as for prioritizing application task instances for execution on cores of manycore processors based at least in part on which of the task instances have available for them the input data, such as ITC data, that they need for executing.
1. A method performed in a data processing system, the method comprising:
receiving, by hardware logic and/or software logic, requests to perform different tasks on behalf of instances of a plurality of programs managed by a data processing system;
identifying, by the hardware logic and/or software logic for each of the instances, communication interdependencies between different processing stages of a set of processing stages of the respective instance;
based on conditions in the data processing system, dynamically varying, by the hardware logic and/or software logic, structures of field-programmable gate arrays used to process different tasks of the instances of the plurality of programs, the structures being dynamically varied by
identifying available field-programmable gate arrays of the data processing system that are available to process different processing stages of requesting instances of respective programs,
based at least on the conditions in the data processing system, identifying selected field-programmable gate arrays from the available field-programmable gate arrays to execute the different processing stages of the requesting instances of the respective programs,
configuring the selected field-programmable gate arrays to process a respective processing stage of a respective requesting instance, and
configuring certain selected field-programmable gate arrays to support communicating, by the task executing on the respective field-programmable gate array, final results to a requesting client over a network in the data processing system.
2. The method of claim 1 , further comprising configuring a portion of the selected field-programmable gate arrays to communicate intermediate results of the different tasks over the network to the certain selected field-programmable gate arrays, the certain selected field-programmable gate arrays using the intermediate results to produce the final results.
3. The method of claim 1 , further comprising:
maintaining availability information identifying availability of the field-programmable gate arrays; and
modifying the availability information to indicate that a particular field-programmable gate array is in use.
4. The method of claim 1 , wherein the conditions comprise changes in demand expressions of the plurality of programs.
5. The method of claim 1 , wherein, for at least one program of the plurality of programs, configuring the selected field-programmable gate arrays results in configuring two or more of the selected field-programmable gate arrays as two or more parallel copies of a given task of the at least one program as a parallelized processing stage.
6. The method of claim 5 , wherein dynamically varying the structures of the field-programmable gate arrays comprises repeatedly configuring the structures for a plurality of iterations to dynamically adjust performance of the different tasks based at least on the conditions.
7. The method of claim 5 , wherein repeatedly configuring the structures comprises, for at least one iteration of the plurality of iterations, deactivating a given copy of the two or more parallel copies in the parallelized processing stage while remaining copies of the two or more parallel copies continue executing the parallelized processing stage, wherein the given copy is deactivated based at least on the conditions.
8. The method of claim 7 , wherein the conditions comprise a decrease in processing load destined for the at least one program.