Semiconductor device
View Patent ↗A semiconductor device of an embodiment includes: a plurality of power lines extending in a first direction; and a plurality of cells arrayed along the first direction and a second direction intersecting the first direction and having a cell height of an integer multiple of a distance between the power lines adjacent to each other in the second direction, the cell height being a dimension in the second direction, wherein the plurality of cells include: a functional cell that contributes to a function of the semiconductor device; and a capacitance cell including a diffusion region of a first conductivity type and a gate electrode stacked above the diffusion region, and functioning as a decoupling capacitor, the capacitance cell is configured as a multi-height cell having a cell height of two or more times the distance, the capacitance cell includes a plurality of overlapping regions that are regions of the gate electrode overlapping the diffusion region in a stacking direction, the overlapping regions being aligned in the second direction, and the plurality of overlapping regions are arranged in one continuous well of a second conductivity type different from the first conductivity type.
1. A semiconductor device comprising:
a plurality of power lines extending in a first direction; and
a plurality of cells arrayed along the first direction and a second direction intersecting the first direction and having a cell height of an integer multiple of a distance between the power lines adjacent to each other in the second direction, the cell height being a dimension in the second direction, wherein
the plurality of cells comprise:
a functional cell that contributes to a function of the semiconductor device; and
a capacitance cell comprising a diffusion region of a first conductivity type and a gate electrode stacked above the diffusion region, and functioning as a decoupling capacitor,
the capacitance cell is configured as a multi-height cell having a cell height of two or more times the distance,
the capacitance cell comprises a plurality of overlapping regions that are regions of the gate electrode overlapping the diffusion region in a stacking direction, the overlapping regions being aligned in the second direction, and
the plurality of overlapping regions are arranged in one continuous well of a second conductivity type different from the first conductivity type.
2. The semiconductor device according to claim 1 , wherein
the capacitance cell has a cell height of an even multiple of the distance, and
both end portions of the capacitance cell in the second direction are arranged in the well.
3. The semiconductor device according to claim 2 , wherein
the capacitance cell is designed by combining at least two types of templates:
a first template arranged in a region of the capacitance cell at an end portion in the first direction and at an end portion in the second direction; and
a second template arranged in a region of the capacitance cell at an inner side relative to the end portion in the first direction and at the end portion in the second direction.
4. The semiconductor device according to claim 3 , wherein
the capacitance cell is designed to have a dimension in the first direction that is adjustable by adjusting a number of the second templates combined.
5. The semiconductor device according to claim 3 , wherein
the capacitance cell has a cell height of four or more times the distance, and
the capacitance cell is designed by combining four types of templates:
the first template;
the second template;
a third template arranged in a region of the capacitance cell at the end portion in the first direction and at an inner side relative to the end portion in the second direction; and
a fourth template arranged in a region of the capacitance cell at the inner side relative to the end portion in the first direction and at the inner side relative to the end portion in the second direction.
6. The semiconductor device according to claim 5 , wherein
the capacitance cell is designed to have a dimension in the first direction that is adjustable by adjusting each of a number of the second templates combined and a number of the fourth templates combined.
7. The semiconductor device according to claim 1 , wherein
the capacitance cell has a cell height of an odd multiple of the distance,
one end portion of the capacitance cell in the second direction is arranged in the well, and
another end portion of the capacitance cell in the second direction is arranged in a first well of the first conductivity type.
8. The semiconductor device according to claim 7 , wherein
the capacitance cell has a cell height of three or more times the distance, and
the capacitance cell is designed by combining six types of templates:
a first template arranged in a region of the capacitance cell at an end portion in the first direction and at one end portion in the second direction;
a second template arranged in a region of the capacitance cell at an inner side relative to the end portion in the first direction and at the one end portion in the second direction;
a third template arranged in a region of the capacitance cell at the end portion in the first direction and at an inner side relative to the end portion in the second direction;
a fourth template arranged in a region of the capacitance cell at the inner side relative to the end portion in the first direction and at the inner side relative to the end portion in the second direction;
a fifth template arranged in a region of the capacitance cell at the end portion in the first direction and another end portion in the second direction; and
a sixth template arranged in a region of the capacitance cell at the inner side relative to the end portion in the first direction and at the another end portion in the second direction.
9. The semiconductor device according to claim 8 , wherein
the capacitance cell is designed to have a dimension in the first direction that is adjustable by adjusting each of a number of the second templates combined, a number of the fourth templates combined, and a number of the sixth templates combined.
10. The semiconductor device according to claim 8 , wherein
the capacitance cell has a cell height of five or more times the distance, and
the capacitance cell is designed by combining the six types of templates:
the first template;
the second template;
the third template;
the fourth template;
the fifth template; and
the sixth template.
11. The semiconductor device according to claim 10 , wherein
the capacitance cell is designed to have a dimension in the first direction that is adjustable by adjusting each of a number of the second templates combined, a number of the fourth templates combined, and a number of the sixth templates combined.
12. The semiconductor device according to claim 1 , wherein
the capacitance cell comprises:
a first region arranged in a second well of the first conductivity type on one end portion side in the first direction; and
a second region arranged in a third well of the first conductivity type on another end portion side in the first direction.
13. The semiconductor device according to claim 12 , wherein
the functional cell comprises:
a third region arranged in the well of the second conductivity type; and
a fourth region arranged in the second well of the first conductivity type and aligned with the third region in the second direction, and
the second well is continuously arranged in the first direction from the first region or the second region of the capacitance cell to the fourth region of the functional cell.
14. The semiconductor device according to claim 13 , wherein
the functional cell comprises a first functional cell and a second functional cell adjacent to the first functional cell in the second direction,
the first functional cell comprises:
the third region on one end portion side in the second direction; and
the fourth region on another end portion side in the second direction, and
the second functional cell comprises:
the fourth region on the one end portion side in the second direction; and
the third region on the another end portion side in the second direction.
15. The semiconductor device according to claim 1 , further comprising:
a wiring layer arranged at a level above the gate electrode and electrically connected to at least one of the gate electrode and the diffusion region.
16. The semiconductor device according to claim 15 , wherein
the wiring layer has a comb teeth-like structure.
17. The semiconductor device according to claim 15 , wherein
the wiring layer comprises a plurality of wiring layers at respective different levels, and
the plurality of wiring layers are connected to each other by a via.