Memory controller, storage device including the memory controller, and method of operating the memory controller and the storage device
A memory controller includes a buffer memory configured to store first meta data and second meta data having a different type from the first meta data, and a cache memory including first and second dedicated areas. The first meta data is cached in the first dedicated area and the second meta data is cached in the second dedicated area.
1. A memory controller for controlling a memory device, the memory controller comprising:
a buffer memory configured to store first meta data and second meta data;
a cache memory including first and second dedicated areas;
a host interface controller configured to generate command segments corresponding to a request of a host, cache the first meta data corresponding to a target command segment among the command segments from the buffer memory to the first dedicated area, and provide the target command segment to a memory operation controller; and
the memory operation controller configured to control an operation of the memory device based on the target command segment, and cache the second meta data corresponding to another command segment to be received after the target command segment among the command segments from the buffer memory to the second dedicated area.
2. The memory controller of claim 1 , wherein the first and second dedicated areas have the same storage capacity size.
3. The memory controller of claim 1 , wherein the first and second dedicated areas have storage capacity sizes proportional to data sizes of the first meta data and the second meta data, respectively.
4. The memory controller of claim 1 , wherein the first and second dedicated areas have storage capacity sizes inversely proportional to data sizes of the first meta data and the second meta data, respectively.
5. The memory controller of claim 1 , further comprising:
a processor configured to request from the buffer memory the first meta data corresponding to a logical address input according to the request of the host and the second meta data of a physical address corresponding to the logical address input according to the request of the host.
6. The memory controller of claim 5 , wherein the first and second dedicated areas have storage capacity sizes proportional to a number of times the processor accesses the first meta data and the second meta data, respectively.
7. The memory controller of claim 5 , wherein the first and second dedicated areas have storage capacity sizes inversely proportional to a number of times the processor accesses the first meta data and the second meta data, respectively.
8. The memory controller of claim 1 , wherein the first meta data includes data chunks having a first data structure, and
the second meta data includes data chunks having a second data structure.
9. The memory controller of claim 1 , wherein the first meta data corresponds to a data storage capacity larger than a data storage capacity corresponding to the second meta data.
10. The memory controller of claim 1 , wherein sizes of the first meta data and the second meta data are in a non-linear relationship with a number of times the first meta data and the second meta data are accessed.
11. A storage device comprising:
a buffer memory configured to store first to N-th meta data;
a cache memory including first to N-th dedicated areas respectively corresponding to areas of the buffer memory in which the first to N-th meta data are stored;
a host interface controller configured to generate command segments corresponding to a request of a host, cache target meta data corresponding to a target command segment among the first to N-th meta data from the buffer memory to a dedicated area corresponding to the target meta data among the first to N-th dedicated areas, and provide the target command segment among the command segments to a memory operation controller; and
the memory operation controller configured to control an operation of a non-volatile memory based on the target command segment, and cache remaining meta data corresponding to remaining command segments other than the target command segment among the command segments from the buffer memory to remaining dedicated areas other than the dedicated area, respectively,
wherein a size of the first to N-th dedicated areas is determined according to a number of times each of the first to N-th meta data is accessed by requests from the host.
12. The storage device of claim 11 , wherein the sizes of the first to N-th dedicated areas are determined according to a pattern in which the first to N-th meta data are accessed.
13. The storage device of claim 11 , wherein the sizes of the first to N-th dedicated areas are determined according to an access probability of each of the first to N-th meta data.
14. The storage device of claim 11 , wherein the sizes of the first to N-th dedicated areas are proportional to a number of accesses of each of the first to N-th meta data.
15. The storage device of claim 11 , wherein the sizes of the first to N-th dedicated areas are inversely proportional to a number of accesses of each of the first to N-th meta data.
16. The storage device of claim 11 , wherein the sizes of the first to N-th dedicated areas are proportional to sizes of the first to N-th meta data, respectively.
17. The storage device of claim 11 , wherein the sizes of the first to N-th dedicated areas are inversely proportional to sizes of the first to N-th meta data, respectively.
18. The storage device of claim 11 , wherein the buffer memory is a dynamic random access memory.
19. The storage device of claim 11 ,
wherein the non-volatile memory is configured to store the first to N-th meta data, and
wherein the non-volatile memory is a NAND flash memory.