IP Library › Granted Patent US 12,142,685
Granted Patent B2
US 12,142,685 · App. 17/197,319 · Granted Nov 12, 2024

FinFET device with high-K metal gate stack

Inventors: Kuo-Cheng Chiang (Hsinchu County, TW); Ka-Hing Fung (Hsinchu County, TW); Chih-Sheng Chang (Hsinchu, TW); Zhiqiang Wu (Hsinchu County, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
H01L29/7851H01L21/02236H01L21/02255H01L21/76224H01L29/0653H01L29/16H01L29/161H01L29/165H01L29/495H01L29/4966H01L29/517H01L29/6681H01L29/66818H01L29/785H01L29/0673
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Quick Facts
Patent No.
US 12,142,685
App. No.
17/197,319
Granted
Nov 12, 2024
Kind
B2
Abstract

Methods are disclosed herein for forming fin-like field effect transistors (FinFETs) that maximize strain in channel regions of the FinFETs. An exemplary method includes forming a fin having a first width over a substrate. The fin includes a first semiconductor material, a second semiconductor material disposed over the first semiconductor material, and a third semiconductor material disposed over the second semiconductor material. A portion of the second semiconductor material is oxidized, thereby forming a second semiconductor oxide material. The third semiconductor material is trimmed to reduce a width of the third semiconductor material from the first width to a second width. The method further includes forming an isolation feature adjacent to the fin. The method further includes forming a gate structure over a portion of the fin, such that the gate structure is disposed between source/drain regions of the fin.

Claims (34)

1. A device comprising:

a fin structure extending from a base substrate layer, the fin structure having a first fin portion having a first width, a second fin portion having a second width disposed over the first fin portion, and a third fin portion having a third width disposed over the second fin portion, wherein:

the first fin portion is a protrusion of the base substrate layer and the second width is greater than the first width and the third width, and

a first composition of the first fin portion is different than a second composition of the second fin portion;

an isolation feature disposed over the base substrate layer, wherein the isolation feature physically contacts first sidewalls of the first fin portion, second sidewalls of the second fin portion, a top surface of the second fin portion, and third sidewalls of the third fin portion; and

wherein the top surface of the second fin portion extends along a fin widthwise direction between the second sidewalls of the second fin portion, the third fin portion is disposed on the top surface of the second fin portion, and the top surface of the second fin portion extends a distance along the fin widthwise direction beyond the third sidewalls of the third fin portion.

2. The device of claim 1 , wherein the first width is substantially uniform from a top to a bottom of the first fin portion and the third width is substantially uniform from a top to a bottom of the third fin portion.

3. The device of claim 1 , wherein the isolation feature physically contacts a bottom portion of the third sidewalls of the third fin portion and the isolation feature does not physically contact an upper portion of the third sidewalls of the third fin portion.

4. The device of claim 1 , wherein a dielectric layer physically contacts a top surface of the third fin portion in a first region of the fin structure and an epitaxial layer physically contacts the top surface of the third fin portion in second regions of the fin structure, wherein the first region of the fin structure is disposed between the second regions of the fin structure.

5. The device of claim 1 , wherein the third width is less than the first width.

6. The device of claim 1 , wherein the first fin portion includes a first semiconductor material, the second fin portion includes a second semiconductor material, and the third fin portion includes a third semiconductor material, wherein the first semiconductor material, the second semiconductor material, and the third semiconductor material include silicon.

7. The device of claim 6 , wherein the second semiconductor material further includes germanium.

8. The device of claim 6 , wherein the second fin portion further includes an oxidized portion of the second semiconductor material, wherein the oxidized portion of the second semiconductor material is disposed between the isolation feature and the second semiconductor material.

9. A device comprising:

a fin structure having a first fin portion having a first width extending from a substrate, a second fin portion having a second width disposed over the first fin portion, and a third fin portion having a third width disposed over the second fin portion;

a first dielectric layer that abuts first sidewalls of the first fin portion, second sidewalls of the second fin portion, and third sidewalls of the third fin portion, wherein:

the first sidewalls of the first fin portion are smooth along a first height thereof, the second sidewalls of the second fin portion are smooth along a second height thereof, and the third sidewalls of the third fin portion are smooth along a third height thereof, and

a sum of the first height, the second height, and the third height is a total height of the fin structure, wherein the second width along an entirety of the second height is greater than the first width along an entirety of the first height and the third width along an entirety of the third height; and

a second dielectric layer that abuts the first dielectric layer and the third sidewalls of the third fin portion, wherein a portion of the first dielectric layer extends from a bottom surface of the second dielectric layer to a top surface of the second fin portion and the portion of the first dielectric layer abuts contacts the bottom surface of the second dielectric layer and the top surface of the second fin portion.

10. The device of claim 9 , wherein a first dielectric material of the first dielectric layer and a second dielectric material of the second dielectric layer are the same.

11. The device of claim 10 , wherein the first dielectric material and the second dielectric material include silicon and oxygen.

12. The device of claim 10 , wherein the first dielectric material includes silicon and nitrogen and the second dielectric material includes oxygen.

13. The device of claim 9 , wherein a first dielectric material of the first dielectric layer and a second dielectric material of the second dielectric layer are different.

14. The device of claim 9 , wherein the first dielectric layer wraps the second fin portion.

15. The device of claim 9 , wherein the first dielectric layer is a portion of an isolation feature and the second dielectric layer is a portion of a gate structure.

16. A device comprising:

a first fin structure and a second fin structure disposed over a substrate, wherein:

the first fin structure and the second fin structure each have an etched substrate fin portion having a first width, a first fin portion having a second width disposed directly on and above the etched substrate fin portion, and a second fin portion having a third width disposed directly on and above the first fin portion, wherein the second width is greater than the first width and the third width, and

the etched substrate fin portion has first linear sidewalls and the second fin portion has second linear sidewalls; and

an isolation feature disposed over the substrate and between the first fin structure and the second fin structure, wherein the isolation feature covers an entirety of first sidewalls of the etched substrate fin portions of the first fin structure and the second fin structure, an entirety of second sidewalls of the first fin portions of the first fin structure and the second fin structure, and lower portions of third sidewalls of the second fin portions of the first fin structure and the second fin structure.

17. The device of claim 16 , wherein the etched substrate fin portions of the first fin structure and the second fin structure have substantially the same height.

18. The device of claim 16 , further comprising a gate structure that covers upper portions of the third sidewalls of the second fin portions of the first fin structure and the second fin structure, wherein the gate structure is disposed directly on the isolation feature.

19. The device of claim 16 , wherein the second fin portions of the first fin structure and the second fin structure have a first height in channel regions of the first fin structure and the second fin structure and a second height in source/drain regions of the first fin structure and the second fin structure, such that the isolation feature covers the lower portions of the third sidewalls of the second fin portions of the first fin structure and the second fin structure in the channel regions and covers the lower portions and the upper portions of the third sidewalls of the second fin portions of the first fin structure and the second fin structure in the source/drain regions.

20. The device of claim 16 , wherein the isolation feature physically contacts laterally extending top surfaces of the first fin portions of the first fin structure and the second fin structure.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 10, 2021
From: CHIANG, KUO-CHENG; FUNG, KA-HING; CHANG, CHIH-SHENG; WU, ZHIQIANG
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 055547/0177 →
Continuity (3)
Continuation 16046541 · Jul 26, 2018
Division 14254035 · Apr 16, 2014
Related Publication 20210202743A1 · Jul 1, 2021