Memory system and method

1. A memory system comprising:

a controller including an interface connectable with a host with cache coherency kept, the controller being configured to:

before the host writes a command to an I/O submission queue, read the I/O submission queue;

after the reading, detect via the interface an invalidation request, the invalidation request being based on writing of the command by the host to the I/O submission queue; and

in response to the invalidation request, acquire the command in the I/O submission queue.

2. The memory system according to claim 1 , wherein after setting the I/O submission queue in initial setting, the controller is configured to perform the reading.

3. The memory system according to claim 2 , wherein the initial setting is setting processing as to initialization processing.

4. The memory system according to claim 3 , wherein the initialization processing is performed upon turning on a power source of the memory system.

5. The memory system according to claim 1 , wherein in response to the invalidation request, the controller is configured to update a tail pointer of the I/O submission queue.

6. The memory system according to claim 1 , wherein the controller is configured to discard the read data.

7. The memory system according to claim 1 , wherein

the interface is in conformity with a CXL standard, and

the controller is configured to transmit a read request of the CXL standard to the host and read the I/O submission queue.

8. The memory system according to claim 7 , wherein the controller is configured to detect the invalidation request of the CXL standard.

9. The memory system according to claim 7 , wherein the read request is a request to read data having a command length and a data length of a cache management unit.

10. The memory system according to claim 9 , wherein the controller is configured to transmit the read request multiple times.

11. A method of controlling a memory system connectable with a host, the method comprising:

connecting to the host with cache coherency kept;

before the host writes a command to an I/O submission queue, reading the I/O submission queue;

after the reading, detecting an invalidation request, the invalidation request being based on writing of the command by the host to the I/O submission queue; and

in response to the invalidation request, acquiring the command written to the I/O submission queue.

12. The method according to claim 11 , wherein after setting the I/O submission queue in initial setting, the reading is performed.

13. The method according to claim 12 , wherein the initial setting is setting processing as to initialization processing.

14. The method according to claim 13 , wherein the initialization processing is performed upon turning on a power source of the memory system.

15. The method according to claim 11 , wherein in response to the invalidation request, the method further comprises updating a tail pointer of the I/O submission queue.

16. The method according to claim 11 , wherein the method further comprises discarding the read data.

17. The method according to claim 11 , wherein

the connecting to the host is in conformity with a CXL standard, and

the method further comprises transmitting a read request of the CXL standard to the host and reading the I/O submission queue.

18. The method according to claim 17 , wherein the detecting includes detecting the invalidation request of the CXL standard.

19. The method according to claim 17 , wherein the read request is a request to read data having a command length and a data length of a cache management unit.

20. The method according to claim 19 , wherein the transmitting includes transmitting the read request multiple times.