Semiconductor memory device
A semiconductor memory device of an embodiment includes: a first inverter including a first P-channel and first N-channel transistors; a second inverter including a second P-channel and second N-channel transistors and being cross-connected to the first inverter; a third P-channel transistor; a third N-channel transistor; a first wiring; a second wiring; a third wiring; a fourth wiring; a fifth wiring; a sixth wiring; and a controller that drives the first to sixth wirings. When writing second-level data that is at a higher potential level than first-level data into the drain of the second P-channel transistor and the drain of the second N-channel transistor, the controller puts one of the fifth wiring and the sixth wiring into a floating state.
1. A semiconductor memory device comprising:
a first inverter including a first P-channel transistor and a first N-channel transistor that are connected in series;
a second inverter including a second P-channel transistor and a second N-channel transistor that are connected in series, the second inverter being cross-connected to the first inverter;
a third P-channel transistor that has one of a source and a drain connected to a drain of the first P-channel transistor and a drain of the first N-channel transistor;
a third N-channel transistor that has one of a source and a drain connected to a drain of the second P-channel transistor and a drain of the second N-channel transistor;
a first wiring that is disposed in a first direction and is connected to the other one of the source and the drain of the third P-channel transistor;
a second wiring that is disposed in the first direction and is connected to a gate of the third N-channel transistor;
a third wiring that is disposed in a second direction intersecting the first direction and is connected to a gate of the third P-channel transistor;
a fourth wiring that is disposed in the second direction and is connected to the other one of the source and the drain of the third N-channel transistor;
a fifth wiring that is disposed in the first direction and is connected to a source of the first N-channel transistor and a source of the second N-channel transistor;
a sixth wiring that is disposed in the second direction and is connected to a source of the first P-channel transistor and a source of the second P-channel transistor; and
a controller that drives the first to sixth wirings,
wherein, when writing second-level data that is at a higher potential level than first-level data into the drain of the second P-channel transistor and the drain of the second N-channel transistor, the controller puts one of the fifth wiring and the sixth wiring into a floating state.
2. The semiconductor memory device according to claim 1 , wherein, when writing the second-level data with the third N-channel transistor and the fourth wiring, the controller puts the fifth wiring into a floating state.
3. The semiconductor memory device according to claim 2 , wherein, when writing the second-level data, the controller applies a second potential level to the second wiring, the third wiring, the fourth wiring, and the sixth wiring, the second potential level being higher than a first potential level applied to the fifth wiring.
4. The semiconductor memory device according to claim 1 ,
wherein, when writing the second-level data with the third P-channel transistor and the first wiring, the controller puts the sixth wiring into a floating state.
5. The semiconductor memory device according to claim 4 , wherein, when writing the second-level data, the controller applies a first potential level to the first wiring, the second wiring, the third wiring, and the fifth wiring, the first potential level being lower than a second potential level applied to the sixth wiring.
6. The semiconductor memory device according to claim 1 , further comprising:
a first switch that is disposed between the fifth wiring and the controller, and is controlled to be in an on-state or an off-state by the controller; and
a second switch that is disposed between the sixth wiring and the controller, and is controlled to be in an on-state or an off-state by the controller.
7. A semiconductor memory device comprising:
a first inverter including a first P-channel transistor and a first N-channel transistor that are connected in series;
a second inverter including a second P-channel transistor and a second N-channel transistor that are connected in series, the second inverter being cross-connected to the first inverter;
a third N-channel transistor that has one of a source and a drain connected to a drain of the first P-channel transistor and a drain of the first N-channel transistor;
a fourth N-channel transistor that has one of a source and a drain connected to a drain of the second P-channel transistor and a drain of the second N-channel transistor;
a first wiring that is disposed in a first direction and is connected to the other one of the source and the drain of the third N-channel transistor;
a second wiring that is disposed in the first direction and is connected to a gate of the fourth N-channel transistor;
a third wiring that is disposed in a second direction intersecting the first direction and is connected to a gate of the third N-channel transistor;
a fourth wiring that is disposed in the second direction and is connected to the other one of the source and the drain of the fourth N-channel transistor;
a fifth wiring that is disposed in the first direction and is connected to a source of the first N-channel transistor;
a sixth wiring that is disposed in the second direction and is connected to a source of the second N-channel transistor; and
a controller that drives the first to sixth wirings,
wherein, when writing second-level data that is at a higher potential level than first-level data into the drain of the second P-channel transistor and the drain of the second N-channel transistor, the controller puts the sixth wiring into a floating state.
8. The semiconductor memory device according to claim 7 , wherein the controller writes the second-level data, using the fourth N-channel transistor and the fourth wiring.
9. The semiconductor memory device according to claim 8 , wherein,
when writing the second-level data, the controller applies a second potential level higher than a first potential level to the second wiring and the fourth wiring, and applies the first potential level to the third wiring, and
before an end of the write operation, the controller applies the first potential level to the sixth wiring.
10. The semiconductor memory device according to claim 7 , wherein, when writing the first-level data into the drain of the second P-channel transistor and the drain of the second N-channel transistor, the controller puts the fifth wiring into a floating state.
11. The semiconductor memory device according to claim 10 , wherein the controller writes the second-level data, using the third N-channel transistor and the first wiring.
12. The semiconductor memory device according to claim 11 , wherein,
when writing the first-level data, the controller applies a second potential level higher than a first potential level to the first wiring and the third wiring, and applies the first potential level to the second wiring and the sixth wiring, and
before an end of the write operation, the controller applies the first potential level to the fifth wiring.
13. The semiconductor memory device according to claim 7 , further comprising:
a first switch that is disposed between the fifth wiring and the controller, and is controlled to be in an on-state or an off-state by the controller; and
a second switch that is disposed between the sixth wiring and the controller, and is controlled to be in an on-state or an off-state by the controller.
14. A semiconductor memory device comprising:
a first inverter including a first P-channel transistor and a first N-channel transistor that are connected in series;
a second inverter including a second P-channel transistor and a second N-channel transistor that are connected in series, the second inverter being cross-connected to the first inverter;
a third P-channel transistor that has one of a source and a drain connected to a drain of the first P-channel transistor and a drain of the first N-channel transistor;
a fourth P-channel transistor that has one of a source and a drain connected to a drain of the second P-channel transistor and a drain of the second N-channel transistor;
a first wiring that is disposed in a first direction and is connected to the other one of the source and the drain of the third P-channel transistor;
a second wiring that is disposed in the first direction and is connected to a gate of the fourth P-channel transistor;
a third wiring that is disposed in a second direction intersecting the first direction and is connected to a gate of the third P-channel transistor;
a fourth wiring that is disposed in the second direction and is connected to the other one of the source and the drain of the fourth P-channel transistor;
a fifth wiring that is disposed in the first direction and is connected to a source of the first P-channel transistor;
a sixth wiring that is disposed in the second direction and is connected to a source of the second P-channel transistor; and
a controller that drives the first to sixth wirings,
wherein, when writing second-level data that is at a lower potential level than first-level data into the drain of the second P-channel transistor and the drain of the second N-channel transistor, the controller puts one of the fifth wiring and the sixth wiring into a floating state.
15. The semiconductor memory device according to claim 14 , wherein, when writing the second-level data with the fourth P-channel transistor and the fourth wiring, the controller puts the sixth wiring into a floating state.
16. The semiconductor memory device according to claim 15 , wherein, when writing the second-level data, the controller applies a second potential level lower than a first potential level to the second wiring and the fourth wiring, and applies the first potential level to the third wiring and the fifth wiring.
17. The semiconductor memory device according to claim 14 , wherein, when writing the second-level data into the drain of the second P-channel transistor and the drain of the second N-channel transistor, the controller puts the fifth wiring into a floating state.
18. The semiconductor memory device according to claim 17 , wherein the controller writes the second-level data, using the third P-channel transistor and the first wiring.
19. The semiconductor memory device according to claim 18 , wherein, when writing the second-level data, the controller applies a first potential level to the first wiring and the second wiring, and applies a second potential level lower than the first potential level to the third wiring.
20. The semiconductor memory device according to claim 14 , further comprising:
a first switch that is disposed between the fifth wiring and the controller, and is controlled to be in an on-state or an off-state by the controller; and
a second switch that is disposed between the sixth wiring and the controller, and is controlled to be in an on-state or an off-state by the controller.