Memory sub-system with dynamic calibration using component-based function(s)

1. A system comprising:

a circuit configured to generate, in response to a data access command received from a controller during a process for calibrating a read level voltage, two or more read results based on reading a set of memory cells using different read voltages, wherein—

the two or more read results are generated as samples used in calibrating the read level voltage initially assigned to read the set of memory cells in response to a read command, and

the different read voltages are separately associated with the initially assigned read level voltage.

2. The system of claim 1 , wherein:

the circuit configured to generate the two or more read results is a first circuit;

further comprising:

a second circuit coupled to the first circuit and configured to receive the data access command from the controller.

3. The system of claim 2 , wherein the first and second circuits and the set of memory cells comprise a memory circuitry.

4. The system of claim 1 , wherein the circuitry is further configured to:

access a control register to identify a test target representative of the set of memory cells; and

identify a read set that corresponds to the test target, wherein the read set includes the two or more read results.

5. The system of claim 4 , wherein the control register comprises:

two or more bits that each correspond to a read level that is specific to a bit value of a page type, and

a control mask set masking one or more bits in the control register separate from the test target.

6. The system of claim 1 , wherein the data access command is configured to operate the circuit to perform multiple read operations on the corresponding set of memory cells with a unique read voltage for each read operation.

7. The system of claim 6 , wherein the circuit is configured to respond to the data access command by outputting to the controller one read result from one of the multiple read operations.

8. The system of claim 7 , wherein the circuit is configured to provide, in response to an output command, one or more remaining read results from a remainder of the multiple read operations.

9. The system of claim 6 , wherein the circuit includes an internal storage circuit configured to store the two or more read results and/or corresponding read voltages.

10. The system of claim 1 , wherein the circuit is configured to implement a dummy read to perform an initial read of the set of memory cells, wherein the initial read is for eliminating transient reactions before generating the two or more read results.

11. A method comprising:

receiving a data access command from a controller during a process for calibrating a read level voltage; and

in response to the received data access command, generating two or more read results based on reading a set of memory cells using different read voltages, wherein—

the two or more read results are generated as samples used in calibrating the read level voltage initially assigned to read the set of memory cells in response to a read command, and

the different read voltages are separately associated with the initially assigned read level voltage.

12. The method of claim 11 , further comprising:

storing the two or more read results; and

providing a first of the two or more read results to the controller at a time different than a second of the two or more read results.

13. The method of claim 12 , wherein providing the first and the second of the two or more read results at different times includes:

providing the first of the two or more read results as a response to the data access command; and

providing the second of the two or more read results as a response to a subsequent command.

14. The method of claim 11 , further comprising:

accessing a control register to identify a test target representative of the a set of memory cells; and

identifying a read set that corresponds to the test target, wherein the read set includes the two or more read results.

15. The method of claim 11 , further comprising performing a dummy read to eliminate transient reactions before generating the two or more read results.

16. The method of claim 11 , further comprising:

based on the two or more read results, determining a set of error rates that includes an error rate for each of the different read voltages; and

dynamically calibrating the read level voltage according to a lowest error rate within the set of error rates.

17. The method of claim 16 , wherein:

the different read voltages include (1) a positive offset level greater than the read level voltage and (2) a negative offset level less than the read level voltage;

the set of error rates includes (1) a positive offset rate corresponding to the positive offset level, (2) a negative offset rate corresponding to the negative offset level, (3) a center rate corresponding to the read level voltage; and

dynamically calibrating the read level voltage includes (1) increasing the read level voltage when the positive offset rate is the lowest error rate or (2) decreasing the read level voltage when the negative offset rate is the lowest error rate.

18. A memory device comprising circuitry configured to:

generate, in response to a data access command received from a controller during a process for calibrating a read level voltage, two or more read results based on reading a set of memory cells using different read voltages that are separately associated with the read level voltage;

determine an error rate for each of the different read voltages based on the two or more read results; and

calibrate the read level voltage based on error rates for the different read voltages.

19. The memory device of claim 18 , wherein the circuitry comprises a memory controller.

20. The memory device of claim 18 , wherein:

the memory device comprises a non-volatile storage device; and

the data access command is different from a read command configured to generate a read result based on reading the set of memory cells using the read level voltage.