Memory device that executes a read operation based on a self-reference scheme
According to one embodiment, a device includes a sense amplifier sensing a first signal based on first data in a cell and a second signal based on second data in the cell. The sense amplifier includes a current mirror causing a first current to flow in a first node connected to the cell and a second current in a second node based on a potential of the first node, a first switch connected to the second node and a third node, a transistor including a terminal connected to the second node and a gate connected to the third node, a second switch connected to the second node and a fourth node, and a circuit connected to the second and third node and causing a third current to flow in the second node based on a potential of the third node.
1. A memory device comprising:
a memory cell; and
a read circuit configured to sense a first signal based on first data in the memory cell, write second data in the memory cell, sense a second signal based on the second data in the memory cell, and read data in the memory cell based on a comparison result between the first signal and the second signal,
wherein:
the read circuit includes a pre-stage sense amplifier circuit configured to sense the first signal and the second signal, and
the pre-stage sense amplifier circuit includes:
a current mirror circuit configured to cause a first current to flow in a first node connected to the memory cell and cause a second current to flow in a second node based on a potential of the first node,
a first switching element including a first terminal connected to the second node and a second terminal connected to a third node,
a first transistor including a third terminal connected to the second node and a first gate connected to the third node,
a second switching element including a fourth terminal connected to the second node and a fifth terminal connected to a fourth node, and
a first circuit connected to the second node and the third node and configured to cause a third current to flow in the second node based on a potential of the third node.
2. The memory device according to claim 1 , wherein:
the first circuit does not cause the third current to flow when the pre-stage sense amplifier circuit senses the first signal, and
the first circuit causes the third current to flow when the pre-stage sense amplifier circuit senses the second signal.
3. The memory device according to claim 1 , wherein:
the first circuit causes the third current to flow when the pre-stage sense amplifier circuit senses the first signal, and
the first circuit does not cause the third current to flow when the pre-stage sense amplifier circuit senses the second signal.
4. The memory device according to claim 1 , wherein the first circuit includes:
a second transistor including a sixth terminal, a seventh terminal connected to the second node, and a second gate connected to the third node, and
a third transistor including an eighth terminal connected to the sixth terminal, a ninth terminal connected to a ground terminal, and a third gate to which a first control signal is supplied.
5. The memory device according to claim 4 , wherein:
the second transistor causes the third current to flow from the second node to the ground terminal when the third transistor is activated based on the first control signal at a first level, and
the second transistor does not cause the third current to flow when the third transistor is inactivated based on the first control signal at a second level.
6. The memory device according to claim 5 , wherein a size of the second gate is smaller than a size of the first gate.
7. The memory device according to claim 1 , wherein a current value of the third current is based on a potential of the third node.
8. The memory device according to claim 1 , wherein:
the read circuit further includes a post-stage sense amplifier circuit configured to compare the first signal with the second signal, and
the post-stage sense amplifier circuit includes a second circuit configured to apply an offset value to one of the first signal of the third node and the second signal of the fourth node.
9. The memory device according to claim 1 , wherein the memory cell includes a magnetoresistance effect element.
10. A memory device comprising:
a memory cell; and
a read circuit configured to sense a first signal based on first data in the memory cell, write second data in the memory cell, sense a second signal based on the second data in the memory cell, and read data in the memory cell based on a comparison result between the first signal and the second signal,
wherein:
the read circuit includes a pre-stage sense amplifier circuit configured to sense the first signal and the second signal, and
the pre-stage sense amplifier circuit includes:
a current mirror circuit configured to cause a first current to flow in a first node connected to the memory cell and cause a second current to flow in a second node based on a potential of the first node,
a first switching element including a first terminal connected to the second node and a second terminal connected to a third node,
a first transistor including a third terminal connected to the second node and a first gate connected to the third node,
a second switching element including a fourth terminal connected to the second node and a fifth terminal connected to a fourth node, and
a first circuit connected to the first node and the second node and configured to cause a third current to flow in the second node based on a potential of the first node.
11. The memory device according to claim 10 , wherein:
the first circuit causes the third current to flow when the pre-stage sense amplifier circuit senses the first signal, and
the first circuit does not cause the third current to flow when the pre-stage sense amplifier circuit senses the second signal.
12. The memory device according to claim 10 , wherein:
the first circuit does not cause the third current to flow when the pre-stage sense amplifier circuit senses the first signal, and
the first circuit causes the third current to flow when the pre-stage sense amplifier circuit senses the second signal.
13. The memory device according to claim 10 , wherein the first circuit includes:
a second transistor including a sixth terminal, a seventh terminal connected to the second node, and a second gate connected to the first node, and
a third transistor including an eighth terminal connected to the sixth terminal, a ninth terminal connected to a power supply terminal, and a third gate to which a first control signal is supplied.
14. The memory device according to claim 13 , wherein:
the second transistor causes the third current to flow from the power supply terminal to the second node when the third transistor is activated based on the first control signal at a first level, and
the second transistor does not cause the third current to flow when the third transistor is inactivated based on the first control signal at a second level.
15. The memory device according to claim 13 , wherein:
the current mirror circuit includes:
a fourth transistor including a tenth terminal connected to the first node and a fourth gate connected to the first node, and
a fifth transistor including a fifth gate connected to the first node and a first terminal connected to the second node, and
the second gate has a smaller size than the fifth gate.
16. The memory device according to claim 10 , wherein a current value of the third current is based on a potential of the first node.
17. The memory device according to claim 10 , wherein:
the read circuit further includes a post-stage sense amplifier circuit configured to compare the first signal with the second signal, and
the post-stage sense amplifier circuit includes a second circuit configured to apply an offset value to one of the first signal of the third node and the second signal of the fourth node.
18. The memory device according to claim 10 , wherein the memory cell includes a magnetoresistance effect element.