Semiconductor packages

1. A semiconductor package comprising:

a first semiconductor chip adhered to a second semiconductor chip by an adhesive layer between the first semiconductor chip and the second semiconductor chip, wherein:

the first semiconductor chip comprises:

a semiconductor substrate; and

a first protection layer and a second protection layer sequentially stacked on the semiconductor substrate,

the first protection layer includes a plurality of holes defined therein, and

the second protection layer is in contact with the adhesive layer.

2. The semiconductor package of claim 1 , wherein the second protection layer fills a portion of the holes defined in the first protection layer.

3. The semiconductor package of claim 1 , wherein each of the plurality of holes has a depth in a vertical direction orthogonal to an upper surface of the first protection layer, and a diameter in a horizontal direction parallel the upper surface of the first protection layer, where the depth is ½ to 1 times the diameter.

4. The semiconductor package of claim 1 , wherein:

the first protection layer has a mesh shaped configuration,

the first protection layer comprises a frame defined by the holes, and

a width of the frame is ½ to 1 times a diameter of the holes, when measured in a first direction.

5. The semiconductor package of claim 1 , wherein:

the first semiconductor chip further comprises a third protection layer, and

the third protection layer is interposed between the semiconductor substrate and the first protection layer.

6. The semiconductor package of claim 5 , wherein the third protection layer comprises a material that is different from that of the first protection layer and is the same as that of the second protection layer.

7. The semiconductor package of claim 5 , wherein a thickness of the third protection layer is greater than a thickness of the first protection layer or a thickness of the second protection layer.

8. The semiconductor package of claim 5 , wherein a part of a top surface of the third protection layer is exposed by the holes, and a bottom surface of the second protection layer contacts part of the top surface of the exposed third protection layer.

9. The semiconductor package of claim 5 , wherein the first semiconductor chip further comprises a through-via penetrating the semiconductor substrate, the through-via extending vertically into the third protection layer and horizontally spaced apart from the second protection layer.

10. The semiconductor package of claim 9 , wherein the level of the top surface of the first protection layer is substantially the same as the level of the top surface of the through-via.

11. A semiconductor package comprising:

a first semiconductor chip;

a second semiconductor chip on the first semiconductor chip; and

an adhesive layer between the first semiconductor chip and the second semiconductor chip, wherein:

the first semiconductor chip comprises:

a semiconductor substrate; and

a plurality of protection layers on the semiconductor substrate,

a topmost layer among the protection layers has a top surface with convex portions and concave portions, and

the convex portions and the concave portions are in contact with the adhesive layer.

12. The semiconductor package of claim 11 , wherein:

the protection layers comprise a first protection layer and a second protection layer which are sequentially stacked on the semiconductor substrate,

the first protection layer comprises a frame defined by a plurality of holes,

the concave portions are vertically overlapped with the holes, and

the convex portions are vertically overlapped with the frame.

13. The semiconductor package of claim 12 , wherein the frame has a width of 1 μm to 2 μm, each of the holes has a diameter of 1 μm to 2 μm, and each of the holes has a depth of 0.25 μm to 2 μm.

14. The semiconductor package of claim 12 , wherein:

the protection layers further comprise a third protection layer between the semiconductor substrate and the first protection layer, and

the first semiconductor chip further comprises a through-via penetrating the semiconductor substrate and the third protection layer.

15. The semiconductor package of claim 14 , wherein the first semiconductor chip further comprises an upper pad connected to the through-via, and the upper pad vertically overlaps the third protection layer and does not overlap the first protection layer.

16. The semiconductor package of claim 14 , wherein a surface area of a top surface of the second protection layer is greater than a surface area of an upper surface of the third protection layer.

17. A semiconductor package comprising:

a first semiconductor chip;

a second semiconductor chip stacked on the first semiconductor chip; and

an adhesive layer between the first semiconductor chip and the second semiconductor, wherein:

the first semiconductor chip comprises:

a semiconductor substrate;

a through-via penetrating the semiconductor substrate;

a first protection layer and a second protection layer, which are sequentially stacked on the semiconductor substrate; and

an upper pad disposed on the second protection layer and connected to the through-via,

the first protection layer is provided to define a plurality of holes, and

a level of a bottom surface of the second protection layer is lower than a level of a top surface of the first protection layer, in a region overlapped with the holes.

18. The semiconductor package of claim 17 , wherein a level of a top surface of the second protection layer is lower than a level of an upper surface of the first protection layer in a region overlapping the holes.

19. The semiconductor package of claim 17 , wherein the adhesive layer comprises a non-conductive film.

20. The semiconductor package of claim 17 , wherein the first semiconductor chip comprises a logic chip and the second semiconductor chip comprises a memory chip.