Inner spacers for gate-all-around semiconductor devices
Semiconductor devices and methods of forming the same are provided. A semiconductor device according to the present disclosure includes a first semiconductor channel member and a second semiconductor channel member over the first semiconductor channel member and a porous dielectric feature that includes silicon and nitrogen. In the semiconductor device, the porous dielectric feature is sandwiched between the first and second semiconductor channel members and a density of the porous dielectric feature is smaller than a density of silicon nitride.
1. A semiconductor structure, comprising:
a plurality of nanostructures disposed over a substrate; and
a plurality of porous inner spacer features interleaving the plurality of nanostructures,
wherein the plurality of porous inner spacer features comprise silicon and nitrogen,
wherein a density of the plurality of porous inner spacer features is smaller than a density of silicon nitride.
2. The semiconductor structure of claim 1 , wherein the plurality of nanostructures are vertically spaced apart from one another.
3. The semiconductor structure of claim 1 , wherein one of the plurality of porous inner spacer features is disposed between a bottommost nanostructure of the plurality of nanostructures and the substrate.
4. The semiconductor structure of claim 1 , wherein a dielectric constant of the plurality of porous inner spacer features is between about 4.9 and about 5.2.
5. The semiconductor structure of claim 1 , wherein the density of the plurality of porous inner spacer features is between about 2.1 g/cm 3 and about 2.3 g/cm 3 .
6. The semiconductor structure of claim 1 , wherein a nitrogen content of the plurality of porous inner spacer features is between about 30% and about 40%.
7. The semiconductor structure of claim 1 , wherein the plurality of porous inner spacer features further comprises carbon.
8. The semiconductor structure of claim 7 , wherein a carbon content of the plurality of porous inner spacer features is between about 3% and about 8%.
9. A semiconductor device, comprising:
a first source/drain feature and a second source/drain feature;
a plurality of nanostructures extending between the first source/drain feature and the second source/drain feature along a direction;
a gate structure wrapping around each of the plurality of nano structures; and
a plurality of porous inner spacer features disposed between the gate structure and the first source/drain feature and between the gate structure and the second source/drain feature,
wherein the plurality of porous inner spacer features comprise silicon and nitrogen,
wherein a density of the plurality of porous inner spacer features is smaller than a density of silicon nitride.
10. The semiconductor device of claim 9 , wherein the plurality of nano structures are vertically spaced apart from one another.
11. The semiconductor device of claim 9 , wherein the plurality of nano structures are interleaved by the plurality of porous inner spacer features.
12. The semiconductor device of claim 9 ,
wherein the plurality of nanostructures are disposed over a substrate,
wherein one of the plurality of porous inner spacer features is disposed between a bottommost nanostructure of the plurality of nanostructures and the substrate.
13. The semiconductor device of claim 9 , wherein a dielectric constant of the plurality of porous inner spacer features is between about 4.9 and about 5.2.
14. The semiconductor device of claim 9 , wherein the density of the plurality of porous inner spacer features is between about 2.1 g/cm 3 and about 2.3 g/cm 3 .
15. The semiconductor device of claim 9 , wherein a nitrogen content of the plurality of porous inner spacer features is between about 30% and about 40%.
16. The semiconductor device of claim 9 , wherein the plurality of porous inner spacer features further comprises carbon.
17. The semiconductor device of claim 16 , wherein a carbon content of the plurality of porous inner spacer features is between about 3% and about 8%.
18. A semiconductor structure, comprising:
a first source/drain feature and a second source/drain feature;
a plurality of nanostructures extending between the first source/drain feature and the second source/drain feature along a direction;
a gate structure wrapping around each of the plurality of nanostructures, the gate structure comprising a top portion over a topmost nanostructure of the plurality of nanostructure;
a plurality of porous inner spacer features disposed between the gate structure and the first source/drain feature and between the gate structure and the second source/drain feature; and
a gate spacer disposed along sidewalls of the top portion of the gate structure, wherein a composition of the gate spacer is different from a composition of the plurality of porous inner spacer features,
wherein the plurality of porous inner spacer features comprise silicon and nitrogen,
wherein a density of the plurality of porous inner spacer features is smaller than a density of silicon nitride.
19. The semiconductor structure of claim 18 , wherein the gate spacer is formed of silicon oxycarbide.
20. The semiconductor structure of claim 18 , wherein the density of the plurality of porous inner spacer features is between about 2.1 g/cm 3 and about 2.3 g/cm 3 .