I/O transmitter circuitry for supporting multi-modes serialization
A I/O transmitter circuitry for supporting multi-modes serialization comprising a serializer, wherein said serializer comprising a multiple FIFO buffers, a multiple flip-flops including a first latch, a second latch, a third flop and a fourth flop, to hold data ready and stage the data for subsequent muxing, a 0-degree shifted clock and a 90-degree shifted clock and a multiplexer, wherein a read pointer reads one bit of data from each of the FIFO buffers, wherein the data is sampled into the respective flip-flops according to frequency of the 0-degree shifted clock and 90-degree shifted clock, wherein the data is outputted by the 0-degree shifted clock and 90-degree shifted clock via the multiplexer.
1. An I/O transmitter circuitry for supporting multi-mode serialization comprising a serializer, wherein said serializer comprising:
multiple FIFO buffers;
multiple flip-flops including a first latch, a second latch, a third flop and a fourth flop, to hold data ready and stage the data for subsequent multiplexing;
a 0-degree shifted clock and a 90-degree shifted clock; and
a multiplexer;
wherein a read pointer reads one bit of data from each of the FIFO buffers;
wherein the data is sampled into the respective flip-flops according to frequency of the 0-degree shifted clock and 90-degree shifted clock; and
wherein the data is outputted by the 0-degree shifted clock and 90-degree shifted clock via the multiplexer.
2. The I/O transmitter circuitry as claimed in claim 1 , wherein the serializer comprises four FIFO buffers, each coupled to one of the multiple flip-flops to support 4-to-1 serialization.
3. The I/O transmitter circuitry as claimed in claim 1 , wherein the serializer further comprises three mux, each of the multiplexer is coupled to the 0-degree shifted clock, the 90-degree shifted clock and the third flop respectively to support 2-to-1 serialization.
4. The I/O transmitter circuitry as claimed in claim 1 , wherein the serializer further comprises an additional mux added to first of the multiple FIFO buffers to support I/O equalization.
5. The I/O transmitter circuitry as claimed in claim 1 , further comprising a bypass path from an external logic and a bypass mux to allow direct asynchronous communication and receiving mode termination.
6. The I/O transmitter circuitry as claimed in claim 1 , further comprising an output enable pin to control output drivers drive strength and termination on a pad.
7. A method of operating an I/O transmitter circuitry for supporting 4-to-1 serialization, the method comprising:
reading bits of data from each FIFO buffers by a read pointer;
capturing an output from each FIFO buffers by two latches and two flops; and
outputting the data from the two latches and two flops by a multiplexer based on a 0-degree shifted clock and a 90-degree shifted clock.
8. The method as claimed in claim 7 , wherein reading bits of data including current data and future data simultaneously from each FIFO buffers by the read pointer for I/O equalization.
9. A method of operating an I/O transmitter circuitry for supporting 2-to-1 serialization, of the method comprising:
reading bits of data from each FIFO buffers by a read pointer; and
capturing an output from each FIFO buffers by a first and second latch and a first and a second flop;
determining 2-to-1 mode serialization;
operating 0-degree shifted clock to drive same clock signals;
replacing a third flop path by said second latch; and
outputting the data from the second latch or a fourth flop by a multiplexer.
10. The method as claimed in claim 9 , wherein shifting data in the FIFO buffers to the left by 1 and doubling the data on every two FIFO locations before reading bits of data for I/O equalization.
11. The method as claimed in claim 10 , wherein reading out future data and current data simultaneously from a FIFO without incurring additional cycle delay.