Semiconductor device and method of manufacturing the same
A semiconductor device includes a first stacked structure having first conductive layers and first insulating layers formed alternately with each other, first semiconductor patterns passing through the first stacked structure, a coupling pattern coupled to the first semiconductor patterns, and a slit passing through the first stacked structure and the coupling pattern.
1. A method of manufacturing a semiconductor device, the method comprising:
forming a sacrificial pattern;
forming a first stacked structure over the sacrificial pattern, wherein the first stacked structure includes first material layers and second material layers formed alternately with each other;
forming first openings passing through the first stacked structure;
removing the sacrificial pattern through the first openings to form a second opening;
forming a multilayer dielectric layer in the first and second openings to fill the second opening;
forming first semiconductor patterns in the first openings;
forming a slit passing through the first stacked structure and the multilayer dielectric layer;
removing a portion of the multilayer dielectric layer through the slit to form a third opening; and
forming a coupling pattern in the third opening.
2. The method of claim 1 , wherein the removing of the portion of the multilayer dielectric layer comprises completely removing the multilayer dielectric layer formed in the second opening, and partially removing the multilayer dielectric layer formed in the first openings.
3. The method of claim 1 , wherein the coupling pattern includes a horizontal portion coupled to lower portions of the first semiconductor patterns and vertical portions protruding from the horizontal portion and surrounding sidewalls of the first semiconductor patterns.
4. The method of claim 3 , wherein a sidewall of the coupling pattern is aligned with an inner wall of the slit.
5. The method of claim 3 , wherein each of the vertical portions surrounds each of the first semiconductor patterns at a non-uniform height.
6. The method of claim 3 , wherein each of the vertical portions has substantially the same thickness as the multilayer dielectric layer.
7. The method of claim 1 , wherein the forming of the coupling pattern comprises:
growing a polysilicon layer from the first semiconductor pattern; and
siliciding the polysilicon layer.
8. The method of claim 1 , wherein the forming of the multilayer dielectric layer comprises:
forming a charge blocking layer in the first and second openings;
forming a data storage layer in the first and second openings, in which the charge blocking layer is formed; and
forming a tunnel insulating layer in the first and second openings, in which the data storage layer is formed, in order to completely fill the second opening.
9. The method of claim 1 , wherein the forming of the multilayer dielectric layer comprises:
forming a charge blocking layer in the first and second openings;
forming a data storage layer in the first and second openings, in which the charge blocking layer is formed, in order to completely fill the second opening; and
forming a tunnel insulating layer in the first openings, in which the data storage layer is formed.
10. The method of claim 1 , further comprising:
forming a second stacked structure including third material layers and fourth material layers formed alternately with each other, before the forming of the sacrificial pattern; and
forming second semiconductor patterns passing through the second stacked structure.
11. A method of manufacturing a semiconductor device, the method comprising:
forming a first stacked structure including first material layers and second material layers formed alternately with each other;
forming first semiconductor patterns passing through the first stacked structure;
forming a sacrificial pattern over the first semiconductor patterns;
forming a second stacked structure over the sacrificial pattern and the first stacked structure, wherein the second stacked structure includes third material layers and fourth material layers formed alternately with each other; and
forming first openings passing through the second stacked structure;
removing the sacrificial pattern through the first openings to form a second opening;
forming a multilayer dielectric layer in the first and second openings to fill the second opening;
forming second semiconductor patterns in the first openings;
forming a slit passing through the second stacked structure, the multilayer dielectric layer and the first stacked structure;
removing a portion of the multilayer dielectric layer through the slit to form a third opening; and
forming a coupling pattern in the third opening.
12. The method of claim 11 , wherein the second semiconductor patterns are coupled to the first semiconductor patterns through the coupling pattern.
13. The method of claim 11 , wherein the coupling pattern includes a horizontal portion coupled to the first semiconductor pattern and the second semiconductor pattern and a vertical portion protruding from the horizontal portion.
14. A method of manufacturing a semiconductor device, the method comprising:
forming a first stacked structure;
forming a first semiconductor pattern passing through the first stacked structure;
forming a sacrificial pattern on the first semiconductor pattern;
forming a second stacked structure over the sacrificial pattern;
forming a first opening passing through the second stacked structure;
removing the sacrificial pattern through the first opening to form a second opening;
forming a dielectric layer in the first opening and the second opening;
forming a second semiconductor pattern in the first opening;
forming a slit passing through the second stacked structure, the dielectric layer and the first stacked structure;
etching the dielectric layer to form a third opening, the third opening exposing the first semiconductor pattern and the second semiconductor pattern; and
forming a coupling pattern in the third opening.
15. The method of claim 14 , wherein the second semiconductor pattern is coupled to the first semiconductor pattern through the coupling pattern.
16. The method of claim 14 , wherein the forming of the sacrificial pattern comprises:
forming an insulating layer on the first semiconductor pattern; and
forming the sacrificial pattern in the insulating layer.
17. A method of manufacturing a semiconductor device, the method comprising:
forming a first stacked structure;
forming a first polysilicon layer passing through the first stacked structure;
forming a sacrificial pattern on the first polysilicon layer;
forming a second stacked structure over the sacrificial pattern;
forming a first opening passing through the second stacked structure;
removing the sacrificial pattern through the first opening to form a second opening;
forming a dielectric layer in the first opening and the second opening;
forming a second polysilicon layer in the first opening;
forming a slit passing through the second stacked structure, the dielectric layer and the first stacked structure;
etching the dielectric layer to form a third opening, the third opening exposing the first polysilicon layer and the second polysilicon layer; and
forming a coupling pattern in the third opening.