Semiconductor memory device

1. A semiconductor memory device comprising:

a first conductive layer and a second conductive layer provided in a first plane; and

at least one memory structure provided between the first conductive layer and the second conductive layer,

wherein the first conductive layer includes:

a first portion, a second portion, and a third portion each extending along a first direction in the first plane, the first portion being provided between the second portion and the third portion in a second direction in the first plane which intersects the first direction;

a fourth portion that connects the first portion and the second portion; and

a fifth portion that connects the first portion and the third portion,

wherein the second conductive layer includes:

a sixth portion, a seventh portion, and an eighth portion each extending along the first direction, the sixth portion being provided between the seventh portion and the eighth portion in the second direction;

a ninth portion that connects the sixth portion and the seventh portion; and

a tenth portion that connects the sixth portion and the eighth portion, and

wherein the second portion is provided between the sixth portion and the eighth portion in the second direction,

wherein the first conductive layer further includes an eleventh portion provided at one end of the first portion in the first direction, and

wherein the eleventh portion is electrically connected to a first contact on an upper surface in the first plane.

2. The semiconductor memory device of claim 1 , wherein the third portion, the first portion, the eighth portion, the second portion, the sixth portion, and the seventh portion are arranged in this order in the second direction.

3. The semiconductor memory device of claim 1 , wherein the first conductive layer and the second conductive layer are electrically separated from each other.

4. The semiconductor memory device of claim 1 , wherein a first end of the second portion and a first end of the eighth portion are provided between the fourth portion and the tenth portion in the first direction.

5. The semiconductor memory device of claim 1 , wherein the fourth portion and the fifth portion are provided at positions different from each other in the first direction.

6. The semiconductor memory device of claim 5 ,

wherein the second portion and the seventh portion are arranged in the second direction,

wherein the third portion and the eighth portion are arranged in the second direction,

wherein the second portion includes a first sub portion and a second sub portion each extending along the first direction, and a third sub portion that is in contact with the fourth portion between the first sub portion and the second sub portion,

wherein the third portion includes a fourth sub portion and a fifth sub portion each extending along the second direction, and a sixth sub portion that is in contact with the fifth portion between the fourth sub portion and the fifth sub portion, and

wherein the first sub portion and the fifth sub portion are arranged in the second direction.

7. The semiconductor memory device of claim 6 , wherein the eighth portion includes a seventh sub portion and an eighth sub portion each extending along the second direction, and a ninth sub portion that is in contact with the tenth portion between the seventh sub portion and the eighth sub portion.

8. The semiconductor memory device of claim 7 , further comprising a first insulator that is in contact with the fourth portion and the eighth portion between the fourth portion and the eighth portion.

9. The semiconductor memory device of claim 8 , further comprising a second insulator that is in contact with the second portion and the tenth portion between the second portion and the tenth portion.

10. The semiconductor memory device of claim 9 , further comprising:

a third insulator that is in contact with the third sub portion and the sixth portion between the third sub portion and the sixth portion; and

a fourth insulator that is in contact with the first portion and the ninth sub portion between the first portion and the ninth sub portion.

11. The semiconductor memory device of claim 9 , further comprising:

a fifth insulator that is in contact with the third sub portion and the sixth portion between the third sub portion and the sixth portion; and

a sixth insulator that is in contact with the first portion and the ninth sub portion between the first portion and the ninth sub portion.

12. The semiconductor memory device of claim 11 , wherein a width of a widest portion of the first insulator and the second insulator in the first direction is narrower than a width of a widest portion of the fifth insulator and the sixth insulator in the first direction.

13. The semiconductor memory device of claim 1 , further comprising:

a seventh insulator provided in the fourth portion; and

an eighth insulator provided in the tenth portion.

14. The semiconductor memory device of claim 1 ,

wherein the second conductive layer further includes a twelfth portion provided at one end of the sixth portion in the first direction on the other end side of the first portion, and

wherein the twelfth portion is electrically connected to a second contact on an upper surface in the first plane.

15. The semiconductor memory device of claim 1 , wherein the at least one memory structure includes:

a first memory structure provided between the first portion and the eighth portion;

a second memory structure provided between the second portion and the eighth portion; and

a third memory structure provided between the second portion and the sixth portion.

16. The semiconductor memory device of claim 15 ,

wherein the first memory structure and the third memory structure are arranged in the second direction, and

wherein the second memory structure is provided at a position different from the first memory structure and the third memory structure in the first direction.

17. The semiconductor memory device of claim 1 ,

wherein the at least one memory structure includes:

a first semiconductor and a second semiconductor;

a first charge storage portion provided between the first conductive layer and the first semiconductor; and

a second charge storage portion provided between the second conductive layer and the second semiconductor.