Voltage clamping circuit for protecting an internal circuitry and a method of operating thereof
A voltage clamping circuit for protecting an internal circuitry comprising an input means for receiving Vin; a p-channel clamping transistor (PCT) coupled to input means for clamping Vin to prevent Vin from falling below a p-channel biasing voltage VbiasP; an n-channel clamping transistor (NCT) coupled to input means for clamping Vin to prevent Vin from rising above an n-channel biasing voltage VbiasN; and a plurality of output means for providing a first output voltage from PCT and a second output voltage from NCT; a p-channel bias circuit including a first, a second and a third bias transistor with each transistor possessing a threshold voltage Vth for providing a p-channel bias voltage to turn on PCT; and an n-channel bias circuit including a fourth, a fifth and a sixth bias transistor with each transistor possessing the threshold voltage Vth for providing an n-channel bias voltage to turn on NCT.
1. A voltage clamping circuit for protecting an internal circuitry comprising:
an input means for receiving an input voltage Vin;
a p-channel clamping transistor coupled to the input means for clamping the input voltage to prevent the input voltage from falling below a p-channel biasing voltage VbiasP;
an n-channel clamping transistor coupled to the input means for clamping the input voltage to prevent the input voltage from rising above an n-channel biasing voltage VbiasN; and
a plurality of output means for providing a first output voltage from the p-channel clamping transistor and a second output voltage from the n-channel clamping transistor;
a p-channel bias circuit including a first bias transistor, a second bias transistor and a third bias transistor with each transistor possessing a threshold voltage Vth for providing a p-channel bias voltage to turn on the p-channel clamping transistor; and
an n-channel bias circuit including a fourth bias transistor, a fifth bias transistor and a sixth bias transistor with each transistor possessing the threshold voltage Vth for providing an n-channel bias voltage to turn on the n-channel clamping transistor;
wherein the first bias transistor is connected to a p-channel biasing line associated with the p-channel biasing voltage VbiasP; the second bias transistor and the third bias transistor are connected in series and to the input means;
wherein the fourth bias transistor is connected to an n-channel biasing line associated with the n-channel biasing voltage VbiasN; the fifth bias transistor and the sixth bias transistor are connected in series and to the input means,
wherein the voltage clamping circuit further comprises:
a p-channel keeping transistor coupled to the p-channel clamping transistor for keeping the first output voltage when the p-channel clamping transistor begins to turn off;
an n-channel keeping transistor coupled to the n-channel clamping transistor for keeping the second output voltage when the n-channel clamping transistor begins to turn off;
a first control circuit for turning on the p-channel keeping transistor; and
a second control circuit for turning on the n-channel keeping transistor,
wherein the first control circuit comprises a first current source configured to limit leakage current of the p-channel clamping transistor and the second control circuit comprises a second current source configured to limit leakage current of the n-channel clamping transistor.
2. The voltage clamping circuit as claimed in claim 1 , wherein the p-channel clamping transistor is a p-type metal-oxide-semiconductor device and the n-channel clamping transistor is an n-type metal-oxide-semiconductor device.
3. The voltage clamping circuit as claimed in claim 1 , wherein the first bias transistor, the second bias transistor and the third bias transistor are further connected to a ground line.
4. The voltage clamping circuit as claimed in claim 1 , wherein the fourth bias transistor, the fifth bias transistor and the sixth bias transistor are further connected to a reference high voltage Vdd.