Method for producing an optoelectronic semiconductor chip and optoelectronic semiconductor chip
In an embodiment a method includes providing a growth substrate comprising a growth surface formed by a planar region having a plurality of three-dimensional surface structures on the planar region, directly applying a nucleation layer of oxygen-containing AlN to the growth surface and growing a nitride-based semiconductor layer sequence on the nucleation layer, wherein growing the semiconductor layer sequence includes selectively growing the semiconductor layer sequence upwards from the planar region such that a growth of the semiconductor layer sequence on surfaces of the three-dimensional surface structures is reduced or non-existent compared to a growth on the planar region, wherein the nucleation layer is applied onto both the planar region and the three-dimensional surface structures of the growth surface, and wherein a selectivity of the growth of the semiconductor layer sequence on the planar region is targetedly adjusted by an oxygen content of the nucleation layer.
1. A method for producing an electronic semiconductor chip, the method comprising:
providing a growth substrate comprising a growth surface formed by a planar region having a plurality of three-dimensional surface structures on the planar region;
directly applying a nucleation layer of oxygen-containing AlN to the growth surface; and
growing a nitride-based semiconductor layer sequence on the nucleation layer,
wherein growing the semiconductor layer sequence comprises selectively growing the semiconductor layer sequence upwards from the planar region such that a growth of the semiconductor layer sequence on surfaces of the three-dimensional surface structures is reduced or non-existent compared to a growth on the planar region,
wherein the nucleation layer is applied onto both the planar region and the three-dimensional surface structures of the growth surface, and
wherein a selectivity of the growth of the semiconductor layer sequence on the planar region is targetedly adjusted by an oxygen content of the nucleation layer.
2. The method according to claim 1 , wherein the three-dimensional surface structures are formed by grooves projecting into the growth substrate.
3. The method according to claim 2 , wherein the grooves are conical or pyramidal grooves.
4. The method according to claim 2 , wherein the grooves have a round cross-section or a polygonal cross-section when the growth surface is viewed from above.
5. The method according to claim 1 , wherein the growth substrate is pre-conditioned in an O 2 plasma such that the growth surface is terminated with oxygen.
6. The method according to claim 1 , wherein the three-dimensional surface structures comprise conical or pyramidal elevations on the planar region.
7. The method according to claim 1 , wherein the semiconductor chip is a light-emitting or light-detecting diode.
8. The method according to claim 1 , wherein the oxygen content of the nucleation layer is more than 10 19 cm −3 .
9. The method according to claim 1 , wherein a weight proportion of oxygen on the nucleation layer is greater than or equal to 0.01%.
10. The method according to claim 9 , wherein the weight proportion of oxygen on the nucleation layer is less than or equal to 10%.
11. The method according to claim 1 , wherein applying the nucleation layer comprises applying a layer of oxygen-free AlN and subsequently oxidizing this layer.
12. A method for producing an electronic semiconductor chip, the method comprising:
providing a growth surface comprising a plurality of three-dimensional surface structures on a planar region;
applying an oxygen-containing nucleation layer to the growth surface; and
growing a nitride-based semiconductor layer sequence on the nucleation layer,
wherein growing the semiconductor layer sequence comprises selectively growing the semiconductor layer sequence such that a growth of the semiconductor layer sequence on surfaces of the three-dimensional surface structures is reduced or non-existent compared to a growth on the planar region,
wherein the nucleation layer is applied onto both the planar region and the three-dimensional surface structures of the growth surface, and
wherein a selectivity of the growth of the semiconductor layer sequence on the planar region is adjusted by an oxygen content of the nucleation layer.
13. The method according to claim 12 , wherein the nucleation layer is formed by a plurality of posts arranged next to each other, and wherein sections of a flat region as well as sections of the three-dimensional surface structures are covered by the posts.
14. The method according to claim 12 , wherein the oxygen content of the nucleation layer is more than 10 19 cm −3 .
15. The method according to claim 12 , wherein a weight proportion of oxygen on the nucleation layer is greater than or equal to 0.01%.
16. The method according to claim 12 , wherein a weight proportion of oxygen on the nucleation layer is less than or equal to 10%.