Signal canceller
The present invention is an architecture and method for radio frequency (RF) simultaneous transmit and receive applications that uses linear and nonlinear modeling to generate a very accurate, wideband analog signal that cancels self-interference before it is digitized by the receiver. In addition to this digitally assisted analog cancellation, another layer of signal cancellation is provided with digital blind source separation. Adaptive signal processing continuously monitors the level of cancellation and updates the processing to provide optimal performance in changing conditions (e.g., rapidly changing frequency content, signal power, temperature, etc.). Signal cancellation can be performed on extremely broadband signals providing high levels of cancellation, enabling a full-duplex RF transceiver. Furthermore, the present invention optionally includes an external signal canceller for cancelling unknown interference such as jamming.
1. A device comprising:
a transmit chain comprising a first digital-to-analog converter (DAC) and a power amplifier, wherein the transmit chain produces an analog transmit signal;
a receiver chain comprising a first analog-to-digital converter (ADC);
a second DAC;
a digital signal processor comprising an adaptive signal cancellation digital signal processing (DSP) algorithm, the digital signal processor coupled to an output of the first ADC and coupled to an input of the second DAC; and
a summer coupled to an output the second DAC and coupled to an input of the first ADC,
wherein the digital signal processor produces a digital cancellation signal, the second DAC converts the digital cancellation signal into an analog digital cancellation signal, the summer receives an analog receive signal comprising a self-interference signal, and the analog digital cancellation signal represents an out-of-phase version of the self-interference signal.
2. The device of claim 1 further comprising a second ADC coupled to an input of the digital signal processor, wherein the second ADC converts the analog receive signal to a digital receive signal.
3. The device of claim 1 , wherein the digital signal processor receives as input a digital transmit signal, the first DAC receives as input the digital transmit signal.
4. The device of claim 1 , wherein the digital signal processor comprises a blind source separation algorithm.
5. The device of claim 1 , wherein the digital signal processor comprises a multi-dimensional compensator.
6. The device of claim 5 , wherein the digital signal processor comprises an adaptive system identification algorithm to optimize coefficients within the multi-dimensional compensator.
7. The device of claim 1 further comprising:
a third ADC, an adaptive signal cancellation digital signal processor, and a third DAC, an output of the third DAC is coupled to an input of the summer; and
a delay receiving the analog receive signal, wherein an output of the delay is coupled to an input of the summer.
8. A device comprising:
a transmit chain comprising a first digital-to-analog converter (DAC) and a power amplifier, wherein the transmit chain produces an analog transmit signal;
a receiver chain comprising a first analog-to-digital converter (ADC);
a second DAC;
a digital signal processor comprising an adaptive signal cancellation digital signal processing (DSP) algorithm, the digital signal processor coupled to an output of the first ADC and coupled to an input of the second DAC; and
a summer coupled to an output the second DAC and coupled to an input of the first ADC,
wherein the digital signal processor comprises a linear finite impulse response filter and an adaptive linear system identification algorithm to optimize linear filter coefficients within the linear finite impulse response filter.
9. A device comprising:
a transmit chain comprising a first digital-to-analog converter (DAC) and a power amplifier, wherein the transmit chain produces an analog transmit signal;
a receiver chain comprising a first analog-to-digital converter (ADC);
a second DAC;
a digital signal processor comprising an adaptive signal cancellation digital signal processing (DSP) algorithm, the digital signal processor coupled to an output of the first ADC and coupled to an input of the second DAC; and
a summer coupled to an output the second DAC and coupled to an input of the first ADC,
wherein the digital signal processor comprises a nonlinear Volterra filter.
10. The device of claim 9 , wherein the digital signal processor comprises an adaptive nonlinear system identification algorithm to optimize nonlinear filter coefficients within the Volterra filter.
11. A method for cancelling self-interference in a transceiver, the method comprising the steps:
receiving an analog receive signal;
combining the analog receive signal with an analog cancellation signal to produce a combined analog signal; wherein the analog cancellation signal represents an out-of-phase version of a self-interference signal introduced by a transmit chain of a transceiver;
converting the combined analog receive signal to a combined digital signal,
inputting the combined digital signal and a digital transmit signal into a digital signal processor implementing an adaptive signal cancellation digital signal processing (DSP) algorithm;
producing, at the digital signal processor, a digital cancellation signal;
converting the digital cancellation signal into the analog cancellation signal; and
adjusting a linear model and a nonlinear model in the adaptive signal cancellation DSP algorithm.
12. The method of claim 11 further comprising the steps of:
converting the analog receive signal to a digital receive signal; and
inputting the digital receive signal into the digital signal processor.
13. The method of claim 11 , wherein the digital signal processor comprises a blind source separation algorithm.
14. The method of claim 11 , wherein the step of adjusting a linear model and a nonlinear model in the adaptive signal cancellation DSP algorithm comprises the step of optimizing linear filter coefficients and nonlinear filter coefficients.
15. The method of claim 11 further comprising the steps of:
producing a delayed analog receive signal from the analog receive signal;
converting the analog receive signal into a digital receive signal;
adjusting an amplitude and a phase of the digital receive signal to produce an adjusted signal; and
combining the delayed analog receive signal and the adjusted signal with the combined analog signal to cancel external interference in the analog receive signal.
16. A method for calibrating a linear model and a nonlinear model in a self-interference signal canceller, the method comprising the steps:
receiving an analog predetermined test signal;
converting the analog predetermined test signal to a digital test signal,
inputting the digital test signal and a digital transmit signal into a digital signal processor implementing an adaptive signal cancellation digital signal processing (DSP) algorithm;
producing, at the digital signal processor, a digital cancellation signal; and
identifying a linear model and a nonlinear model in the adaptive signal cancellation DSP algorithm.
17. The method of claim 16 , further comprising the steps of:
converting the digital cancellation signal to an analog cancellation signal;
combining the analog predetermined test signal with the analog cancellation signal to produce a combined analog signal, wherein the analog cancellation signal represents an out-of-phase version of a self-interference signal introduced by a transmit chain of a transceiver;
converting the combined analog receive signal to a combined digital signal,
inputting the combined digital signal and the digital transmit signal into the digital signal processor; and
adjusting the linear model and the nonlinear model in the adaptive signal cancellation DSP algorithm.