Electronic devices and methods of manufacturing the same
An electronic device includes a seed layer including a two-dimensional (2D) material, and a ferroelectric layer on the seed layer. The ferroelectric layer is configured to be aligned in a direction in which a (111) crystal direction is perpendicular to a top surface of a substrate on which the seed layer is located and/or a top surface of the seed layer.
1. An electronic device, comprising:
a substrate;
a seed layer on the substrate, the seed layer including a two-dimensional (2D) material; and
a ferroelectric layer on the seed layer, the ferroelectric layer configured to be aligned within a range of ±30 degrees with respect to a direction in which a (111) crystal direction is perpendicular to a top surface of the substrate,
wherein the seed layer includes a metallic 2D material.
2. The electronic device of claim 1 , wherein the seed layer has a lattice constant having a magnitude that is in a range of about 90% to about 110% with respect to a magnitude of a lattice constant of the ferroelectric layer.
3. The electronic device of claim 1 , wherein the seed layer includes at least one of 1T-MoTe 2 , 1T-WTe 2 , 2H—MoTe 2 , 2H—WTe 2 , 1T-ZrS 2 , 1T-HfS 2 , 2H—ZrS 2 , 2H—HfS 2 , 2H—CrTe 2 , 2H—HfSe 2 , 1T-PdS 2 , 1T-PtS 2 , 2H—SnS 2 , 2H—TiSe 2 , 2H—VTe 2 , 2H—NbSe 2 , or GaS.
4. The electronic device of claim 1 , wherein the seed layer has a thickness in a range of about 0.3 nm to about 100 nm.
5. The electronic device of claim 1 , wherein the ferroelectric layer includes an oxide of at least one of silicon (Si), aluminum (Al), hafnium (Hf), or zirconium (Zr).
6. The electronic device of claim 5 , wherein the ferroelectric layer includes a dopant, the dopant including at least one of hafnium (Hf), silicon (Si), aluminum (Al), zirconium (Zr), yttrium (Y), lanthanum (La), gadolinium (Gd), or strontium (Sr).
7. The electronic device of claim 1 , wherein the ferroelectric layer has ferroelectric or anti-ferroelectric properties.
8. The electronic device of claim 1 , wherein the seed layer has a hexagonal lattice structure.
9. The electronic device of claim 1 , further comprising:
an upper layer on the ferroelectric layer, the upper layer including at least one of a dielectric, silicon oxide (SiO), aluminum oxide (AlO), hafnium oxide (HfO), zirconium oxide (ZrO), yttrium oxide (YO), lanthanum oxide (LaO), or strontium oxide (SrO).
10. The electronic device of claim 9 , wherein the upper layer includes at least one of Hf, Si, Al, Zr, Y, La, Gd, or Sr.
11. The electronic device of claim 9 , wherein the upper layer includes a metal, a metal nitride, or a metal oxide.
12. The electronic device of claim 9 , wherein the upper layer includes at least one of Si, germanium (Ge), a thin film semiconductor, an oxide semiconductor, a III-V-group compound, a 2D material, transition metal dichalcogenides, a quantum dot, a colloidal QD, a nanocrystal, or an organic material.
13. The electronic device of claim 1 , wherein the seed layer has a lattice constant in a range of about 2.16 to about 3.96.
14. The electronic device of claim 1 , wherein the seed layer has an energy band gap greater than or equal to about 0.2 and less than or equal to about 1.8.
15. A method of manufacturing an electronic device, the method comprising:
forming a seed layer on a substrate, wherein the seed layer includes a two-dimensional (2D) material; and
forming a ferroelectric layer on the seed layer, wherein the ferroelectric layer is aligned within a range of ±30 degrees with respect to a direction in which a (111) crystal direction of the ferroelectric layer is perpendicular to a top surface of the substrate,
wherein the seed layer includes a metallic 2D material.
16. The method of claim 15 , further comprising crystallizing the ferroelectric layer through an annealing process.
17. The method of claim 15 , wherein the seed layer has a lattice constant having a magnitude that is in a range of about 90% to about 110% with respect to a magnitude of a lattice constant of the ferroelectric layer.
18. The method of claim 15 , wherein the seed layer includes at least one of 1T-MoTe 2 , 1T-WTe 2 , 2H—MoTe 2 , 2H—WTe 2 , 1T-ZrS 2 , 1T-HfS 2 , 2H—ZrS 2 , 2H—HfS 2 , 2H—CrTe 2 , 2H—HfSe 2 , 1T-PdS 2 , 1T-PtS 2 , 2H—SnS 2 , 2H—TiSe 2 , 2H—VTe 2 , 2H—NbSe 2 , or GaS.
19. The method of claim 15 , wherein the ferroelectric layer includes an oxide of at least one of silicon (Si), aluminum (Al), hafnium (Hf), or zirconium (Zr).
20. A method of manufacturing a computing device, the method comprising:
manufacturing an electronic device according to the method of claim 16 ; and
forming the computing device based on incorporating the electronic device into a computing device component.
21. A system for manufacturing an electronic device, the system comprising:
a process chamber including a pedestal or chuck configured to structurally support one or more devices or layers in the process chamber;
a plurality of composition sources and a plurality of control devices, each composition source coupled to the process chamber via a separate control device, each control device configured to control a supply of a separate material held in a separate coupled composition source to the process chamber; and
processing circuitry configured to control at least the plurality of control devices to manufacture the electronic device based on
forming a seed layer on a substrate, wherein the seed layer includes a two-dimensional (2D) material, and
forming a ferroelectric layer on the seed layer, wherein the ferroelectric layer is aligned within a range of ±30 degrees with respect to a direction in which a (111) crystal direction of the ferroelectric layer is perpendicular to a top surface of the substrate.