Semiconductor package structure

1. A semiconductor package structure, comprising:

a substrate;

a redistribution layer over the substrate;

a first semiconductor component over the redistribution layer and comprising a through via;

a conductive via over the first semiconductor component;

a plurality of bump structures over the conductive via, wherein the conductive via is in direct contact with the plurality of bump structures and the through via;

a conductive pillar adjacent to the first semiconductor component, wherein the first semiconductor component and the conductive pillar are surrounded by a molding material; and

a second semiconductor component over the molding material, wherein the second semiconductor component is electrically coupled to and contacting a second conductive via, is electrically coupled to the conductive pillar through the second conductive via that is directly contacting the conductive pillar, and is electrically coupled to the redistribution layer through the conductive pillar.

2. The semiconductor package structure as claimed in claim 1 , wherein the first semiconductor component is electrically coupled to the second semiconductor component through the plurality of bump structures.

3. The semiconductor package structure as claimed in claim 2 , wherein the second semiconductor component is electrically coupled to the redistribution layer through the plurality of bump structures, the conductive via, and the through via.

4. The semiconductor package structure as claimed in claim 1 , wherein the through via is electrically coupled to the redistribution layer.

5. The semiconductor package structure as claimed in claim 4 , wherein the plurality of bump structures are between the first semiconductor component and the second semiconductor component, and the second semiconductor component is electrically coupled to the redistribution layer through the plurality of bump structures and the through via.

6. The semiconductor package structure as claimed in claim 1 , further comprising an adhesive layer between the first semiconductor component and the second semiconductor component.

7. The semiconductor package structure as claimed in claim 6 , wherein the first semiconductor component is electrically coupled to the second semiconductor component through the conductive pillar and the redistribution layer.

8. The semiconductor package structure as claimed in claim 1 , wherein a sidewall of the molding material is substantially coplanar with a sidewall of the redistribution layer.

9. The semiconductor package structure as claimed in claim 8 , wherein the sidewall of the molding material is substantially coplanar with a sidewall of the second semiconductor component.

10. A semiconductor package structure, comprising:

a substrate;

a redistribution layer over the substrate;

a first semiconductor component over the redistribution layer and having a first surface and a second surface opposite to the first surface;

a through via in the first semiconductor component and extending from the first surface of the first semiconductor component to the second surface of the first semiconductor component;

a conductive via formed within a passivation layer over the through via;

a plurality of bump structures over the conductive via, wherein the conductive via is in direct contact with the plurality of bump structures and the through via; and

a second semiconductor component over the first semiconductor component, wherein the second semiconductor component is electrically coupled to the first semiconductor component through the plurality of bump structures and electrically coupled to the redistribution layer through the plurality of bump structures and the through via.

11. The semiconductor package structure as claimed in claim 10 , wherein a sidewall of the first semiconductor component is substantially coplanar with a sidewall of the second semiconductor component.

12. The semiconductor package structure as claimed in claim 11 , wherein the sidewall of the first semiconductor component is substantially coplanar with a sidewall of the redistribution layer.

13. The semiconductor package structure as claimed in claim 10 , further comprising a plurality of conductive structures between the redistribution layer and the substrate, wherein the plurality of conductive structures are electrically coupled to the redistribution layer and a wiring structure of the substrate.

14. The semiconductor package structure as claimed in claim 10 , further comprising a plurality of conductive terminals below the substrate, wherein the plurality of conductive terminals are electrically coupled to a wiring structure of the substrate.