IP Library Granted Patent US 11,990,480
Granted Patent B2
US 11,990,480 · App. 17/209,314 · Granted May 21, 2024

Display device and array substrate

Inventors: Masanobu Ikeda (Minato-ku, JP); Yasuhiro Kanaya (Minato-ku, JP); Yoshinori Aoki (Minato-ku, JP)
Assignee: Japan Display Inc.
H01L27/124H01L25/167H01L27/1248
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Quick Facts
Patent No.
US 11,990,480
App. No.
17/209,314
Granted
May 21, 2024
Kind
B2
Abstract

A display device includes a substrate, a plurality of pixels provided to the substrate, a light emitting element and a plurality of transistors provided to each of the pixels, a plurality of signal lines configured to supply a signal to the pixels, a power supply line configured to supply a drive potential to the pixels, a first metal layer, a second metal layer, and a third metal layer provided in different layers in a direction perpendicular to the substrate, a first insulating film provided between the first metal layer and the second metal layer, and a second insulating film provided between the second metal layer and the third metal layer.

Claims (40)

1. A display device comprising:

a substrate;

a plurality of pixels provided to the substrate;

a light emitting element and a plurality of transistors provided to each of the pixels;

a plurality of signal lines configured to supply a signal to the pixels;

a power supply line configured to supply a drive potential to the pixels;

a first metal layer, a second metal layer, and a third metal layer provided in different layers in a first direction perpendicular to the substrate;

a first insulating film provided between the first metal layer and the second metal layer; and

a second insulating film provided between the second metal layer and the third metal layer,

wherein

the transistors each comprise:

a semiconductor layer provided to the substrate; and

a gate electrode formed in the first metal layer and provided in a region overlapping the semiconductor layer,

the signal lines are formed in the third metal layer and electrically coupled to the transistors,

the power supply line is formed in the second metal layer,

the power supply line overlaps at least one of the signal lines in planar view,

the first insulating film includes a first part overlapping the power supply line and a second part not overlapping the power supply line,

the thickness of the first part is smaller than the thickness of the second part,

an upper surface of the first part is closer to the substrate than an upper surface of the second part, in the first direction, and

relative permittivity of the first insulating film is higher than relative permittivity of the second insulating film.

2. The display device according to claim 1 , wherein sheet resistance of the power supply line is equal to or lower than sheet resistance of the signal lines.

3. The display device according to claim 1 , wherein

the plurality of transistors in each pixel include:

a first transistor configured to supply an electric current to the light emitting element; and

a second transistor coupled to the first transistor,

the display device comprises gate lines formed in the first metal layer and coupled to the gate electrodes of the second transistors, and

sheet resistance of the signal lines is equal to or lower than sheet resistance of the gate lines.

4. The display device according to claim 3 , wherein

one gate electrode is provided overlapping the semiconductor layer of each of the first transistors, and

two gate electrodes are provided overlapping the semiconductor layer of each of the second transistors.

5. The display device according to claim 3 , wherein at least one of the signal lines is electrically coupled to the semiconductor layer of the second transistor via a relay electrode formed in the second metal layer.

6. The display device according to claim 3 , wherein

a contact hole passing through the first insulating film and the second insulating film in the first direction is formed, and

at least one of the signal lines is electrically coupled to the semiconductor layer of the second transistor through the contact hole.

7. The display device according to claim 3 , further comprising:

coupling wiring formed in the third metal layer, wherein

the gate electrodes of the first transistors are electrically coupled to the semiconductor layers of the second transistors via the coupling wiring.

8. The display device according to claim 3 , further comprising:

coupling wiring formed in the second metal layer, wherein

the gate electrodes of the first transistors are electrically coupled to the semiconductor layers of the second transistors via the coupling wiring.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 23, 2021
From: IKEDA, MASANOBU; KANAYA, YASUHIRO; AOKI, YOSHINORI
To: JAPAN DISPLAY INC.
Reel/Frame 055680/0699 →
Priority Claims (1)
JP 2018-179814 · Sep 26, 2018 · national
Continuity (2)
Continuation PCTJP2019033808 · Aug 28, 2019
Related Publication 20210210513A1 · Jul 8, 2021