Channel encoding method and apparatus

1. A channel encoding method, comprising:

obtaining A to-be-encoded information bits;

mapping the A to-be-encoded information bits and L cyclic redundancy check (CRC) bits to a first bit sequence based on an interleaving sequence, wherein the L CRC bits are obtained based on the A to-be-encoded information bits and a CRC polynomial, wherein the interleaving sequence is obtained from a prestored interleaving sequence table based on a number of the A to-be-encoded information bits to be interleaved and not based on CRC data, and wherein, in the interleaving sequence table, each information bit length corresponds uniquely to one and only one interleaving sequence; and

performing channel encoding on the first bit sequence.

2. The method according to claim 1 , wherein before the mapping of the A to-be-encoded information bits and L CRC bits to a first bit sequence based on an interleaving sequence, the method further comprises:

performing CRC encoding on the A to-be-encoded information bits based on the CRC polynomial to obtain the L CRC bits.

3. The method according to claim 1 , wherein the mapping of the A to-be-encoded information bits and L CRC bits to a first bit sequence based on an interleaving sequence comprises:

mapping the A to-be-encoded information bits and the L CRC bits to the first bit sequence based on the interleaving sequence and according to the following rule:

if a to-be-mapped bit is an information bit, mapping the to-be-mapped bit to a corresponding location based on an index of the to-be-mapped bit in the interleaving sequence; or

if a to-be-mapped bit is a CRC bit, determining a value of the to-be-mapped bit based on A and the CRC polynomial, and mapping the to-be-mapped bit to a corresponding location.

4. The method according to claim 3 , wherein the determining of a value of the to-be-mapped bit based on A and the CRC polynomial, and mapping the to-be-mapped bit to a corresponding location comprises:

determining, based on A and the CRC polynomial, all information bits checked by using the to-be-mapped bit; and

performing addition modulo 2 on all the information bits checked by using the to-be-mapped bit to obtain the value of the to-be-mapped bit and mapping the to-be-mapped bit to the corresponding location.

5. The method according to claim 3 , wherein the determining of a value of the to-be-mapped bit based on A and the CRC polynomial, and mapping the to-be-mapped bit to a corresponding location comprises:

identifying a correspondence that is between at least one CRC bit and at least one information bit and that corresponds to A from a prestored table of correspondences between CRC bits and information bits, wherein the correspondence between at least one CRC bit and at least one information bit indicates all information bits checked by using each of the L CRC bits, and the correspondence between at least one CRC bit and at least one information bit is obtained based on an information bit length and the CRC polynomial;

determining, based on the correspondence that is between at least one CRC bit and at least one information bit and that corresponds to A, all information bits checked by using the to-be-mapped bit; and

performing addition modulo 2 on all the information bits checked by using the to-be-mapped bit to obtain the value of the to-be-mapped bit and mapping the to-be-mapped bit to the corresponding location.

6. The method according to claim 1 , wherein when A= 32 , the interleaving sequence in the prestored interleaving sequence table is:

0, 2, 3, 5, 7, 10, 11, 12, 14, 15, 18, 19, 21, 24, 26, 30, 31, 32, 1, 4, 6, 8, 13, 16, 20, 22, 25, 27, 33, 9, 17, 23, 28, 34, 29, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, wherein 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, and 55 are indexes of CRC bits.

7. A channel encoding apparatus, comprising:

a memory configured to store a program instruction; and

a processor configured to execute the program instruction to:

obtain A to-be-encoded information bits;

map the A to-be-encoded information bits and L cyclic redundancy check (CRC) bits to a first bit sequence based on an interleaving sequence, wherein the L CRC bits are obtained based on the A to-be-encoded information bits and a CRC polynomial, wherein the interleaving sequence is obtained from a prestored interleaving sequence table based on a number of the A to-be-encoded information bits to be interleaved and not based on CRC data, and wherein in the interleaving sequence table, each information bit length corresponds uniquely to one and only one interleaving sequence; and

perform channel encoding on the first bit sequence.

8. The apparatus according to claim 7 , wherein the processor is further configured to:

before mapping the A to-be-encoded information bits and the L CRC bits to the first bit sequence based on the interleaving sequence, perform CRC encoding on the A to-be-encoded information bits based on the CRC polynomial to obtain the L CRC bits.

9. The apparatus according to claim 7 , wherein the processor is further configured to:

map the A to-be-encoded information bits and the L CRC bits to the first bit sequence based on the interleaving sequence and according to the following rule:

if a to-be-mapped bit is an information bit, mapping the to-be-mapped bit to a corresponding location based on an index of the to-be-mapped bit in the interleaving sequence; or

if a to-be-mapped bit is a CRC bit, determining a value of the to-be-mapped bit based on A and the CRC polynomial, and mapping the to-be-mapped bit to a corresponding location.

10. The apparatus according to claim 9 , wherein the processor is further configured to:

determine, based on A and the CRC polynomial, all information bits checked by using the to-be-mapped bit; and

perform addition modulo 2 on all the information bits checked by using the to-be-mapped bit to obtain the value of the to-be-mapped bit and map the to-be-mapped bit to the corresponding location.

11. The apparatus according to claim 9 , wherein the processor is further configured to:

identify a correspondence that is between at least one CRC bit and at least one information bit and that corresponds to A from a prestored table of correspondences between CRC bits and information bits, wherein the correspondence between at least one CRC bit and at least one information bit indicates all information bits checked by using each of the L CRC bits, and the correspondence between at least one CRC bit and at least one information bit is obtained based on an information bit length and the CRC polynomial;

determine, based on the correspondence that is between at least one CRC bit and at least one information bit and that corresponds to A, all information bits checked by using the to-be-mapped bit; and

perform addition modulo 2 on all the information bits checked by using the to-be-mapped bit to obtain the value of the to-be-mapped bit and map the to-be-mapped bit to the corresponding location.

12. The apparatus according to claim 7 , wherein when A=32, the interleaving sequence in the prestored interleaving sequence table is:

0, 2, 3, 5, 7, 10, 11, 12, 14, 15, 18, 19, 21, 24, 26, 30, 31, 32, 1, 4, 6, 8, 13, 16, 20, 22, 25, 27, 33, 9, 17, 23, 28, 34, 29, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, wherein 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, and 55 are indexes of CRC bits.

13. The apparatus according to claim 7 , wherein the apparatus is a chip.

14. A non-transitory computer-readable storage medium embodying computer program code that, when executed by a channel encoding apparatus, is configured to configure the channel encoding apparatus to:

obtain A to-be-encoded information bits;

map the A to-be-encoded information bits and L cyclic redundancy check (CRC) bits to a first bit sequence based on an interleaving sequence, wherein the L CRC bits are obtained based on the A to-be-encoded information bits and a CRC polynomial, wherein the interleaving sequence is obtained from a prestored interleaving sequence table based on a number of the A to-be-encoded information bits to be interleaved and not based on CRC data, and wherein, in the interleaving sequence table, each information bit length corresponds uniquely to one and only one interleaving sequence; and

perform channel encoding on the first bit sequence.

15. The non-transitory computer-readable storage medium according to claim 14 , wherein the channel encoding apparatus is further configured to:

before mapping the A to-be-encoded information bits and the L CRC bits to the first bit sequence based on the interleaving sequence, perform CRC encoding on the A to-be-encoded information bits based on the CRC polynomial to obtain the L CRC bits.

16. The non-transitory computer-readable storage medium according to claim 14 , wherein the channel encoding apparatus is further configured to:

map the A to-be-encoded information bits and the L CRC bits to the first bit sequence based on the interleaving sequence and according to the following rule:

if a to-be-mapped bit is an information bit, mapping the to-be-mapped bit to a corresponding location based on an index of the to-be-mapped bit in the interleaving sequence; or

if a to-be-mapped bit is a CRC bit, determining a value of the to-be-mapped bit based on A and the CRC polynomial, and mapping the to-be-mapped bit to a corresponding location.

17. The non-transitory computer-readable storage medium according to claim 16 , wherein the channel encoding apparatus is further configured to:

determine, based on A and the CRC polynomial, all information bits checked by using the to-be-mapped bit; and

perform addition modulo 2 on all the information bits checked by using the to-be-mapped bit to obtain the value of the to-be-mapped bit and map the to-be-mapped bit to the corresponding location.

18. The non-transitory computer-readable storage medium according to claim 16 , wherein the channel encoding apparatus is further configured to:

identify a correspondence that is between at least one CRC bit and at least one information bit and that corresponds to A from a prestored table of correspondences between CRC bits and information bits, wherein the correspondence between at least one CRC bit and at least one information bit indicates all information bits checked by using each of the L CRC bits, and the correspondence between at least one CRC bit and at least one information bit is obtained based on an information bit length and the CRC polynomial;

determine, based on the correspondence that is between at least one CRC bit and at least one information bit and that corresponds to A, all information bits checked by using the to-be-mapped bit; and

perform addition modulo 2 on all the information bits checked by using the to-be-mapped bit to obtain the value of the to-be-mapped bit and map the to-be-mapped bit to the corresponding location.

19. The non-transitory computer-readable storage medium according to claim 15 , wherein when A=32, the interleaving sequence in the prestored interleaving sequence table is:

0, 2, 3, 5, 7, 10, 11, 12, 14, 15, 18, 19, 21, 24, 26, 30, 31, 32, 1, 4, 6, 8, 13, 16, 20, 22, 25, 27, 33, 9, 17, 23, 28, 34, 29, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, wherein 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, and 55 are indexes of CRC bits.