High-speed multi-port memory supporting collision
A multi-port memory is provided that supports collision between a read port and a write port to the same multi-port bitcell. A sense amplifier reads a data bit from a multi-port bitcell when a write port to the multi-port bitcell is addressed during a system clock signal. Should a read port to the multi-port bitcell be addressed during the same system clock signal, a multiplexer selects for an output bit from the sense amplifier.
1. A multi-port memory, comprising:
a multi-port bitcell including a first read port having a first read port bit line, the multi-port bitcell further including a pair of write port bit lines and a second read port having a second read port bit line;
a sense amplifier coupled to the pair of write port bit lines;
a first inverter coupled to the first read port bit line;
a first multiplexer configured to select between a data output bit from the sense amplifier and a data output bit from the first inverter to provide a selected data output bit;
a second inverter coupled to the second read port bit line; and
a second multiplexer configured to select between a complement data output bit from the sense amplifier and a complement data output bit from the second inverter to provide a selected complement data output bit.
2. The multi-port memory of claim 1 , further comprising:
a data latch configured to latch the selected data output bit and the selected complement data output bit.
3. The multi-port memory of claim 1 , further comprising:
an address comparator configured to detect a collision responsive to a read port address being the same as a write port address and to detect a lack of a collision responsive to the read port address being different from the write port address; and
a read word line controller configured to assert a read port word line to the first read port responsive to a detection of the lack of the collision and to not assert the read port word line responsive a detection of the collision.
4. The multi-port memory of claim 3 , wherein the read word line controller is further configured to assert a pre-charge signal responsive to the detection of the lack of the collision and to not assert the pre-charge signal responsive to the detection of the collision.
5. The multi-port memory of claim 4 , further comprising a transistor coupled between the first read port bit line and a power supply node for a power supply voltage, wherein the transistor is configured to switch on responsive to an assertion of the pre-charge signal and to turn off responsive to a non-assertion of the pre-charge signal.
6. The multi-port memory of claim 5 , wherein the transistor comprises a p-type metal-oxide-semiconductor (PMOS) transistor.
7. The multi-port memory of claim 3 , wherein the multi-port bitcell comprises a pair of cross-coupled inverters configured to drive a data output node and a complement data output node, and wherein the first read port further includes an access transistor configured to be controlled by the read port word line.
8. The multi-port memory of claim 7 , wherein the first read port further includes a second transistor coupled between ground and a terminal of the access transistor, and wherein a gate of the second transistor is coupled to the data output node, and wherein the multi-port memory is integrated into a cellular telephone.
9. The multi-port memory of claim 1 , further comprising:
a write driver configured to drive the pair of write bit line responsive to a bit to be written to the multi-port bitcell after a completion of a sense operation by the sense amplifier.