Integrated circuit structure and manufacturing method thereof
A method includes depositing a dielectric cap over a gate structure. A source/drain contact is formed over a source/drain region after forming the dielectric cap. A top of the dielectric cap is doped to form a doped region in the dielectric cap. After doping the top of the dielectric cap, a etch stop layer and an interlayer dielectric (ILD) layer are deposited over the dielectric cap. A via opening is formed to extend though the ILD layer and the etch stop layer to expose the source/drain contact. A source/drain via is filled in the via opening.
1. A method comprising:
depositing a dielectric cap over a gate structure;
forming a source/drain contact over a source/drain region after forming the dielectric cap;
doping a top of the dielectric cap to form a doped region in the dielectric cap, wherein the top of the dielectric cap is doped after forming the source/drain contact;
after doping the top of the dielectric cap, depositing a etch stop layer and an interlayer dielectric (ILD) layer over the dielectric cap;
forming a via opening extending though the ILD layer and the etch stop layer to expose the source/drain contact; and
filling a source/drain via in the via opening.
2. The method of claim 1 , wherein the top of the dielectric cap is doped with oxygen ions.
3. The method of claim 1 , wherein the top of the dielectric cap is doped with germanium, argon, xenon, and/or boron.
4. The method of claim 1 , further comprising annealing the doped region of the dielectric cap.
5. The method of claim 1 , wherein a dopant depth of the doped region is in a range from about 1 Angstroms to about 50 Angstroms.
6. The method of claim 1 , wherein forming the via opening is such that the via opening further exposes the doped region of the dielectric cap.
7. The method of claim 1 , wherein forming the via opening comprises:
performing a first etching process to form the via opening extending though the ILD layer and expose a top surface of the etch stop layer; and
performing a second etching process to deepen the via opening such that the via opening extends through the etch stop layer.
8. The method of claim 7 , wherein the first etching process is a plasma etching process using a plasma generated from a hydrogen-free gaseous mixture.
9. The method of claim 7 , wherein the second etching process is a plasma etching process using a plasma generated from a hydrogen-containing gaseous mixture.
10. The method of claim 1 , wherein a ratio of a depth of the doped region to a maximal thickness of the dielectric cap is in a range from about 3% to about 60%.
11. A device comprising:
a gate structure;
a dielectric cap over the gate structure and comprising a doped region and an un-doped region between the gate structure and the doped region;
a source/drain contact adjacent to the gate structure and in contact with a sidewall of the doped region of the dielectric cap;
an interlayer dielectric (ILD) layer over the doped region of the dielectric cap and the source/drain contact; and
a source/drain via in the ILD layer and electrically connected to the source/drain contact.
12. The device of claim 11 , wherein the doped region comprises oxygen, germanium, argon, xenon, boron, or combinations thereof.
13. The device of claim 11 , wherein the un-doped region of the dielectric cap is thicker than the doped region of the dielectric cap.
14. The device of claim 11 , wherein the doped region of the dielectric cap has an oxygen concentration gradient.
15. The device of claim 11 , further comprising an etch stop layer in contact with the doped region of the dielectric cap, the source/drain contact, and the ILD layer.
16. A method comprising:
providing a gate structure with a gate spacer surrounding the gate structure;
etching back the gate structure and the gate spacer;
forming a dielectric cap over the gate structure and the gate spacer;
forming source/drain contacts on opposite sides of the dielectric cap;
doping the dielectric cap to form a doped region in a top portion of the dielectric cap, wherein a ratio of a depth of the doped region to a maximal thickness of the dielectric cap is in a range from about 3% to about 60%;
depositing a dielectric layer over the doped region of the dielectric cap and the source/drain contacts;
forming a via opening in the dielectric layer to expose one of the source/drain contacts; and
forming a source/drain via in the via opening.
17. The method of claim 16 , wherein the doped region of the dielectric cap is spaced apart from the gate spacer.
18. The method of claim 16 , wherein the doped region of the dielectric cap is in contact with the source/drain contacts.
19. The method of claim 16 , wherein dopants of the doped region of the dielectric cap are oxygen.
20. The method of claim 16 , wherein forming the via opening in the dielectric layer is such that the via opening further exposes the doped region of the dielectric cap.