ESD protection circuit
An ESD protection circuit is provided, including a negative ESD protection module and a positive ESD protection module, where the negative ESD protection module includes a first resistor, a charging capacitor, a first field effect transistor, and a second field effect transistor, and the positive ESD protection module includes a fourth field effect transistor. When a negative ESD event occurs, there is a comparatively large transient voltage at a gate of a P-type enhanced GaN power device relative to a source of the P-type enhanced GaN power device. Therefore, a displacement current from the source to the gate of the P-type enhanced GaN power device is generated on the charging capacitor. A voltage drop generated by the displacement current on the first resistor may enable the first field effect transistor and the second field effect transistor to form a path when the first field effect transistor is turned on.
1. An electrostatic discharge (ESD) protection circuit, comprising:
a negative ESD protection circuit and a positive ESD protection circuit, wherein the positive ESD protection circuit and the negative ESD protection circuit are connected in parallel, and the positive ESD protection circuit and the negative ESD protection circuit are connected to a P-type enhanced GaN power device;
wherein the negative ESD protection circuit comprises a first resistor, a charging capacitor, a first field effect transistor, and a second field effect transistor; a first end of the first resistor is connected to a gate of the P-type enhanced GaN power device, and a second end of the first resistor is connected to a gate of the first field effect transistor and a first end of the charging capacitor; a drain of the first field effect transistor is connected to the gate of the P-type enhanced GaN power device, and a source of the first field effect transistor is connected to a drain of the second field effect transistor; and a gate and a source of the second field effect transistor are connected to a source of the P-type enhanced GaN power device; and
wherein the positive ESD protection circuit comprises a fourth field effect transistor, wherein a gate and a drain of the fourth field effect transistor are connected to the gate of the P-type enhanced GaN power device, and a source of the fourth field effect transistor is connected to the source of the P-type enhanced GaN power device.
2. The ESD protection circuit according to claim 1 , wherein a clamp diode string is further disposed on the positive ESD protection circuit, an anode of the clamp diode string is connected to the gate of the P-type enhanced GaN power device, and a cathode of the clamp diode string is connected to the source of the P-type enhanced GaN power device.
3. The ESD protection circuit according to claim 2 , wherein a second resistor and a fifth field effect transistor are further disposed between the cathode of the clamp diode string and the P-type enhanced GaN power device; the cathode of the clamp diode string is connected to a first end of the second resistor and a gate of the fifth field effect transistor; a drain of the fifth field effect transistor is connected to the source of the fourth field effect transistor; a second end of the second resistor and a source of the fifth field effect transistor are connected to the source of the P-type enhanced GaN power device.
4. The ESD protection circuit according to claim 1 , wherein, responsive to a negative ESD, the fourth field effect transistor is transitioned to an off state.
5. The ESD protection circuit according to claim 4 , wherein, responsive to the negative ESD, a voltage is generated across the first resistor that causes the first field effect transistor to conduct.
6. The ESD protection circuit according to claim 5 , wherein, responsive to a positive ESD, the second field effect transistor is transitioned to the off state.
7. An ESD protection circuit, comprising a positive ESD protection circuit and a negative ESD protection circuit, wherein:
the negative ESD protection circuit comprises a first resistor, a charging capacitor, and a first field effect transistor; a first end of the first resistor is connected to a drain of the first field effect transistor and a gate of a P-type enhanced GaN power device, and a second end of the first resistor is connected to a gate of the first field effect transistor and a first end of the charging capacitor; and a second end of the charging capacitor and a source of the first field effect transistor are connected to a source of the P-type enhanced GaN power device;
the positive ESD protection circuit comprises a sixth field effect transistor, wherein a source of the sixth field effect transistor is connected to the source of the P-type enhanced GaN power device, and both a gate and a drain of the sixth field effect transistor are connected to the drain of the first field effect transistor; and
a third field effect transistor is further connected between the first resistor and the first field effect transistor, wherein a gate of the third field effect transistor is connected to the first end of the first resistor, a source of the third field effect transistor is connected to the drain of the first field effect transistor, and a drain of the third field effect transistor is connected to the gate of the P-type enhanced GaN power device.
8. The ESD protection circuit according to claim 7 , wherein a clamp diode string is further disposed on the positive ESD protection circuit, an anode of the clamp diode string is connected to the gate of the P-type enhanced GaN power device, and a cathode of the clamp diode string is connected to the first end of the first resistor and the gate of the third field effect transistor.
9. The ESD protection circuit according to claim 8 , wherein a third resistor is further disposed between the clamp diode string and the first resistor, a first end of the third resistor is connected to the cathode of the clamp diode string and the gate of the third field effect transistor, and a second end of the third resistor is connected to the first end of the first resistor and the drain of the first field effect transistor.
10. The ESD protection circuit according to claim 7 , wherein, responsive to a negative ESD, a voltage is generated across the first resistor that causes the first field effect transistor to conduct.
11. The ESD protection circuit according to claim 10 , wherein, responsive to the negative ESD, a voltage is generated on the third resistor that causes the third field effect transistor to conduct.