Non-dissipative output voltage transition for an isolated switching power converter

1. A flyback converter, comprising:

a transformer having a primary-side winding and a secondary-side winding;

an input capacitor coupled to the primary-side winding;

an output capacitor coupled to the secondary-side winding;

a synchronous rectifier switch transistor coupled to the secondary-side winding; and

a controller configured to cycle the synchronous rectifier switch transistor during an output voltage transition period to lower an output voltage for the flyback converter through a transfer of energy from the output capacitor to the input capacitor, wherein the controller is further configured to cycle the synchronous rectifier switch transistor in response to a detection of a triggering event to begin the output voltage transition period.

2. The flyback converter of claim 1 , wherein the controller is further configured to detect the triggering event in response to a portable device disconnect from the flyback converter.

3. The flyback converter of claim 1 , wherein the controller is further configured to detect the triggering event in response to a command from a portable device connected to the flyback converter.

4. The flyback converter of claim 1 , wherein the controller is further configured to cycle the synchronous rectifier switch transistor with a constant switching period during the output voltage transition period.

5. The flyback converter of claim 4 , wherein the controller is further configured to cycle the synchronous rectifier switch transistor with a constant on-time period during the output voltage transition period.

6. The flyback converter of claim 5 , wherein a ratio of the constant on-time period to the constant switching period is less than one-half.

7. The flyback converter of claim 1 , wherein the controller is a secondary-side controller, the flyback converter further comprising:

a ground-isolating channel;

a power switch transistor coupled to the primary-side winding; and

a primary-side controller, wherein the secondary-side controller is configured to transmit an alert through the ground-isolating channel to stop the primary-side controller from cycling the power switch transistor during the output voltage transition period.

8. The flyback converter of claim 7 , wherein the ground-isolating channel comprises an optoisolator.

9. The flyback converter of claim 7 , wherein the power switch transistor is configured to conduct a resetting current through a body diode during off-time periods of the synchronous rectifier switch transistor in the output voltage transition period.

10. The flyback converter of claim 1 , wherein the controller is further configured to cycle the synchronous rectifier switch transistor during the output voltage transition period to lower the output voltage for the flyback converter to a default level.

11. The flyback converter of claim 10 , wherein the default level is approximately five volts.

12. The flyback converter of claim 1 , wherein the controller is a secondary-side controller, the flyback converter further comprising:

a power switch transistor coupled to the primary-side winding; and

a primary-side controller configured to cycle on the power switch transistor during off-time periods of the synchronous rectifier switch transistor in the output voltage transition period.

13. A method of operating a flyback converter comprising:

during a normal mode of operation, cycling a power switch transistor so that energy flows from an input capacitor to an output capacitor;

initiating an output voltage transition mode of operation in response to a disconnect of a portable device from the flyback converter or in response to a command from the portable device; and

during the output voltage transition mode of operation, cycling a synchronous rectifier switch transistor so that energy flows from the output capacitor to the input capacitor to lower an output voltage.

14. The method of claim 13 , further comprising:

ceasing the cycling of the synchronous rectifier switch transistor to end the output voltage transition mode of operation in response to the output voltage lowering to a default level.

15. The method of claim 14 , wherein the default level is approximately five volts.

16. The method of claim 13 , further comprising:

conducting a resetting current through a body diode of the power switch transistor in response to a cycling off of the synchronous rectifier switch transistor during the output voltage transition mode of operation.

17. The method of claim 13 , further comprising:

driving a gate voltage of a power switch transistor in response to a cycling off of the synchronous rectifier switch transistor to cause the power switch transistor to conduct a resetting current during the output voltage transition mode of operation.