Semiconductor memory device and method of operating the same

1. A semiconductor memory device, comprising:

a memory cell array including a plurality of memory cells, each of which stores N bits of data, where N is a natural number of 2 or more; and

a peripheral circuit configured to perform a program operation on a physical page including memory cells selected from among the plurality of memory cells,

wherein the peripheral circuit is configured to receive data corresponding to N logical pages and program the data corresponding to the N logical pages to the physical page based on a logic code,

wherein the logic code is determined to equalize numbers of sensing operations required to read the data corresponding to the N logical pages, respectively, and

wherein weak read levels are assigned, according to the logic code, to read data of a logical page, among the N logical pages, for which the number of sensing operations is smallest.

2. The semiconductor memory device according to claim 1 , wherein N is 3 and each of the selected memory cells is determined to belong to any one of eight threshold voltage states.

3. The semiconductor memory device according to claim 2 , wherein:

first to seventh read levels are used to distinguish the eight threshold voltage states, and

the weak read levels are a first read level and a seventh read level, among the first to seventh read levels.

4. The semiconductor memory device according to claim 3 , wherein the logic code is configured such that:

a second read level, a fourth read level, and a sixth read level are used to read data corresponding to a first logical page among the three logical pages,

a third read level and a seventh read level are used to read data corresponding to a second logical page among the three logical pages, and

a first read level and a fifth read level are used to read data corresponding to a third logical page among the three logical pages.

5. The semiconductor memory device according to claim 1 , wherein N is 5 and each of the selected memory cells is determined to belong to any one of 32 threshold voltage states.

6. The semiconductor memory device according to claim 5 , wherein:

first to 31-st read levels are used to distinguish the 32 threshold voltage states from each other, and

the weak read levels are a first read level, a second read level, a 30-th read level, and a 31-st read level.

7. The semiconductor memory device according to claim 6 , wherein the logic code is configured such that:

ninth, eleventh, fourteenth, 25-th, 27-th, and 30-th read levels are used to read data corresponding to a first logical page among the five logical pages,

second, sixth, eighth, eighteenth, 22-nd, and 24-th read levels are used to read data corresponding to a second logical page among the five logical pages,

first, seventh, sixteenth, nineteenth, 21-st, and 28-th read levels are used to read data corresponding to a third logical page among the five logical pages,

fourth, twelfth, twentieth, 26-th, 29-th, and 31-st read levels are used to read data corresponding to a fourth logical page among the five logical pages, and

third, fifth, tenth, thirteenth, fifteenth, seventeenth, and 23-rd read levels are used to read data corresponding to a fifth logical page among the five logical pages.

8. The semiconductor memory device according to claim 1 , wherein the logic code is a gray code.

9. A method of operating a semiconductor memory device including a plurality of memory cells, wherein each of the memory cells stores N bits of data and memory cells included in one physical page store data corresponding to N logical pages, the method comprising:

receiving data corresponding to N logical pages from a memory controller;

determining threshold voltage states of memory cells selected from among the plurality of memory cells based on the data corresponding to the N logical pages and a logic code; and

programming the selected memory cells based on the determined threshold voltage states,

wherein the logic code is determined to equalize numbers of sensing operations required to read the data corresponding to the N logical pages, respectively, and

wherein weak read levels are assigned, according to the logic code, to read data of a logical page, among the N logical pages, for which the number of sensing operations is smallest.

10. The method according to claim 9 , wherein N is 3 and each of the selected memory cells is determined to belong to any one of eight threshold voltage states.

11. The method according to claim 10 , wherein, among the three logical pages:

two sensing operations are assigned to read a first logical page;

two sensing operations are assigned to read a second logical page; and

three sensing operations are assigned to read a third logical page.

12. The method according to claim 11 , wherein the weak read levels are assigned to read the first and second logical pages.

13. The method according to claim 9 , wherein N is 5 and each of the selected memory cells is determined to belong to any one of 32 threshold voltage states.

14. The method according to claim 13 , wherein, among the five logical pages:

six sensing operations are assigned to read a first logical page;

six sensing operations are assigned to read a second logical page;

six sensing operations are assigned to read a third logical page;

six sensing operations are assigned to read a fourth logical page; and

seven sensing operations are assigned to read a fifth logical page.

15. The method according to claim 14 , wherein the weak levels are assigned to read the first and second logical pages.

16. A semiconductor memory device, comprising:

a memory cell array including a plurality of memory cells, each of which stores N bits of data, where N is a natural number of 2 or more; and

a peripheral circuit configured to perform a program operation on a physical page including memory cells selected from among the plurality of memory cells,

wherein the peripheral circuit is configured to receive data corresponding to N logical pages and program the data corresponding to the N logical pages to the physical page based on a logic code,

wherein the logic code is determined to equalize numbers of sensing operations required to read the data corresponding to the N logical pages, respectively, and

wherein, among a first read level to a (2 N −1)-th read level having sequential magnitudes to distinguish 2 N threshold voltage states from each other, the first read level that is a lowest read level and the (2 N −1)-th read level that is a highest read level are assigned to read data corresponding to different logical pages among the data corresponding to the N logical pages.

17. The semiconductor memory device according to claim 16 , wherein:

N is 3 and each of the selected memory cells is determined to belong to any one of eight threshold voltage states, and

a first read level and a seventh read level, among the first read level to the seventh read levels having sequential values, are assigned to read data corresponding to different logical pages.

18. The semiconductor memory device according to claim 16 , wherein:

N is 5 and each of the selected memory cells is determined to belong to any one of 32 threshold voltage states, and

a first read level and a 31-st read level, among the first read level to the 31-st read levels having sequential values, are assigned to read data corresponding to different logical pages.

19. The semiconductor memory device according to claim 18 , wherein, among the first read level to the 31-st read level, the first read is level, a second read level, a 30-th read level, and the 31-st read level are assigned to read different logical pages, respectively.