Yield improvements for three-dimensionally stacked neural network accelerators
Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for three-dimensionally stacked neural network accelerators. In one aspect, a method includes obtaining data specifying that a tile from a plurality of tiles in a three-dimensionally stacked neural network accelerator is a faulty tile. The three-dimensionally stacked neural network accelerator includes a plurality of neural network dies, each neural network die including a respective plurality of tiles, each tile has input and output connections. The three-dimensionally stacked neural network accelerator is configured to process inputs by routing the input through each of the plurality of tiles according to a dataflow configuration and modifying the dataflow configuration to route an output of a tile before the faulty tile in the dataflow configuration to an input connection of a tile that is positioned above or below the faulty tile on a different neural network die than the faulty tile.
1. A circuit, comprising:
a plurality of dies vertically stacked on top of each other,
each die including a plurality of tiles,
each of the plurality of tiles comprising a multiplexer,
wherein the multiplexer of each tile is connected to outputs of a plurality of other tiles in the plurality of tiles and controls which output of the outputs of the plurality of other tiles the tile receives as an input;
wherein the plurality of tiles includes a first tile on a first die that has been determined to be a faulty tile; and
wherein a dataflow configuration is configured to route the output of a tile on the first die prior to the faulty tile on the first die in an initial dataflow configuration to an input of a tile on a second different die and vertically adjacent to the faulty tile on the first die instead of to an input of the faulty tile on the first die.
2. The circuit of claim 1 , further comprising inductive coupling between tiles on different dies enabling communication between the tiles on different dies.
3. The circuit of claim 1 , further comprising, for each multiplexer, a respective controller coupled to the multiplexer, wherein the controller is configured to transmit instructions to the multiplexer to designate an active input for the multiplexer.
4. The circuit of claim 1 , further comprising, for each wafer, a respective controller coupled to each multiplexer included on the wafer, wherein the controller is configured to transmit instructions to each multiplexer included on the wafer to designate an active input for each multiplexer.
5. The circuit of claim 1 , further comprising, a controller coupled to each multiplexer, wherein the controller is configured to transmit instructions to each multiplexer to designate an active input for each multiplexer.
6. The circuit of claim 1 , wherein to define the dataflow configuration to route the output of the tile on the first die prior to the faulty tile on the first die in the initial dataflow configuration to an input of a tile on the second different die and vertically adjacent to the faulty tile on the first die, the input of the multiplexer of the tile on the second different die and vertically adjacent to the faulty tile on the first die is set to receive the output of the tile on the first die prior to the faulty tile on the first die in the initial dataflow configuration.
7. The circuit of claim 1 , wherein the faulty tile has been disabled.
8. The circuit of claim 7 , wherein disabling the faulty tile comprises removing power that is distributed to the faulty tile.
9. The circuit of claim 7 , wherein disabling the faulty tile comprises turning off a clock that is unique to the faulty tile.
10. The circuit of claim 1 , wherein each tile communicates with one or more adjacent tiles to create a ring network of tiles, wherein the ring network is configured such that each functional tile within the ring network receives and transfers data.