Memory bandwidth control in a core
Techniques for controlling bandwidth in a core are described. An exemplary core includes a memory bandwidth monitor per thread local to the core, each thread's local bandwidth monitor to at least allocate bandwidth for memory requests originating from the thread according to a class of service level stored in a field of quality of service (QoS) model-specific register (MSR), the class of service level pointed to by a class of service field in a platform quality of service MSR; and execution resources to support execution of at least one thread of the core.
1 . An apparatus comprising:
a plurality of per thread quality of service (QoS) model specific registers (MSRs), wherein each QoS MSR is associated with a single thread;
a platform level MSR to index into the thread QOS MSRs;
a memory bandwidth monitor per thread local to a core, each thread's local bandwidth monitor to at least allocate bandwidth for memory requests originating from the thread according to a value for a first class of service stored in a field of its associated thread QoS MSR of the plurality of thread QoS MSRs, the class of service pointed to by the platform level MSR, wherein each of the thread QoS MSRs is to store a value for a plurality of classes of service including the value for the first class of service; and
execution resources to support execution of at least one thread of the core.
2 . The apparatus of claim 1 , wherein each field of the QOS MSR is 8-bit in size.
3 . The apparatus of claim 1 , wherein, upon a context switch to a second thread from a first thread, the platform quality of service MSR is to be written to update the class of service field.
4 . The apparatus of claim 3 , wherein the second thread is associated with a QoS MSR.
5 . The apparatus of claim 1 , further comprising:
a last level cache and wherein the memory request is to the last level cache.
6 . The apparatus of claim 1 , further comprising:
a memory bandwidth monitor per thread external to the core to monitor memory requests from the core and to provide feedback regarding bandwidth based on software allocation and bandwidth monitoring.
7 . The apparatus of claim 1 , wherein the memory request is to a main memory.
8 . The apparatus of claim 1 , wherein the bandwidth is to be adjusted in a non-linear fashion.
9 . The apparatus of claim 1 , wherein the bandwidth is to be adjusted in a linear fashion.
10 . The apparatus of claim 1 , wherein support for per thread memory bandwidth is enumerated in a CPUID leaf.
11 . The apparatus of claim 1 , wherein the core further comprises:
a local queue to receive memory requests from a thread of the core, wherein a number of available entries in the local queue is to be configured based on the class of service value of the QOS MSR.
12 . The apparatus of claim 1 , wherein the core further comprises:
an external queue to receive memory requests from outside of the core, wherein a number of available entries in the external queue is to be configured based on the class of service value of the QOS MSR.
13 . A system comprising:
a core including:
a plurality of per thread quality of service (QOS) model specific registers (MSRs),
wherein each QoS MSR is associated with a single thread;
a platform level MSR to index into the thread QOS MSRs;
a memory bandwidth monitor per thread local to a core, each thread's local bandwidth monitor to at least allocate bandwidth for memory requests originating from the thread according to a value for a first class of service stored in a field of its associated thread QoS MSR of the plurality of thread QoS MSRs, the class of service pointed to by the platform level MSR, wherein each of the thread QoS MSRs is to store a value for a plurality of classes of service including the value for the first class of service, and
execution resources to support execution of at least one thread of the core; and
memory coupled to the core.
14 . The system of claim 13 , wherein each field of the QOS MSR is 8-bit in size.
15 . The system of claim 13 , wherein, upon a context switch to a second thread, the platform quality of service MSR is to be written to update the class of service field.
16 . The system of claim 15 , further comprising:
a QOS MSR for the second thread.
17 . The system of claim 13 , wherein the core further comprises:
a last level cache and the request to the last level cache.
18 . The system of claim 13 , further comprising:
a memory bandwidth monitor per thread external to the core to monitor memory requests from the core and to provide feedback regarding bandwidth based on software allocation and bandwidth monitoring.
19 . The system of claim 13 , wherein the bandwidth is to be adjusted in a non- linear fashion.
20 . The system of claim 13 , wherein the bandwidth is to be adjusted in a linear fashion.