Heterostructure oxide semiconductor vertical gate-all-around (VGAA) transistor and methods for making the same
A semiconductor transistor comprises a channel structure comprising a channel region and two source/drain regions located on respective sides of the channel region, wherein the channel region and the two source/drain regions are stacked up along a first direction. A gate structure surrounds the channel region.
1. A semiconductor transistor, comprising:
a channel structure extending up from a contact metal layer in a first direction comprising:
a channel region; and
two source/drain regions located on respective sides of the channel region, wherein the channel region and the two source/drain regions are stacked up along the first direction; and
a gate structure surrounding the channel region,
wherein the channel structure and the gate structure terminate at a same plane extending orthogonally to the first direction.
2. The transistor of claim 1 , wherein a length of the gate structure in the first direction is greater than a length of the channel region in the first direction.
3. The transistor of claim 2 , wherein a length of the channel structure in the first direction is greater than the length of the channel region in the first direction.
4. The transistor of claim 2 , wherein the channel region comprises Indium Gallium Zinc Oxide (IGZO).
5. The transistor of claim 2 , wherein the transistor further comprises a dielectric layer surrounding the channel structure between the channel structure and the gate structure.
6. The transistor of claim 5 , wherein the dielectric layer, the channel structure, and the gate structure terminate at the same plane extending orthogonally to the first direction.
7. The transistor of claim 5 , wherein the dielectric layer extends a distance in the first direction beyond the same plane extending orthogonally to the first direction.
8. The transistor of claim 2 , wherein a thickness of each of the two source/drain regions in the first direction is different.
9. A semiconductor device, comprising:
a memory element; and
a transistor connected to the memory element in series, the memory element and transistor stacked up along a first direction,
wherein the transistor comprises:
a channel structure comprising:
a channel region; and
two source/drain regions located on respective sides of the channel region,
wherein the channel region and the two source/drain regions are stacked up along the first direction;
a gate structure surrounding the channel region, wherein a length of the gate structure in the first direction is greater than a length of the channel region;
a first contact structure disposed on a bottom surface of the channel structure and connected to one of the source/drain regions; and
a second contact structure disposed on a top surface of the channel structure and connected to one of the source/drain regions, wherein the channel structure and the gate structure terminate at a same plane extending orthogonally to the first direction.
10. The device of claim 9 , wherein the channel region comprises Indium Gallium Zinc Oxide (IGZO) and each of the two source/drain regions comprise Indium Tin Oxide (ITO).
11. The device of claim 10 , wherein the transistor further comprises:
a dielectric layer surrounding the channel structure between the channel structure and the gate structure; and
a spacer oxide layer separating the first contact structure from the dielectric layer and the gate structure.
12. The device of claim 11 , wherein the gate structure is located in between a horizontal plane including a top surface of the first contact structure and a horizontal plane including a bottom surface of the second contact structure.
13. The device of claim 9 , wherein a diameter of the channel structure is uniform along the first direction.
14. The device of claim 9 , wherein a diameter of the channel region along the first direction is less than a diameter of each of the two source/drain regions along the first direction.
15. A semiconductor structure comprising:
a contact metal layer located over a substrate;
a vertical stack including, from bottom to top, a first source/drain region comprising a first semiconducting oxide material, a channel region comprising a second semiconducting oxide material, and a second source/drain region, wherein the first semiconducting metal oxide material is selected from ITO, InZnO, or oxygen deficient IGZO, and the second semiconducting metal oxide material comprises a stoichiometric oxide selected from InGaZnO 4 , Ga 2 O 3 , In 2 O 3 , or ZnO;
a dielectric layer comprising a first portion that laterally surrounds the vertical stack and a second portion that extends horizontally;
a gate electrode laterally surrounding the first portion of the dielectric layer;
a contact structure laterally surrounded by an interlayer dielectric (ILD) and contacting a top surface of the second source/drain region; and
a spacer oxide layer disposed between, and contacting each of, the contact metal layer and the second portion of the dielectric layer.
16. The semiconductor structure of claim 15 , wherein the channel region has a first width, the first source/drain region has a second width that is greater than the first width.
17. The semiconductor structure of claim 16 , wherein the second source/drain region has the second width.
18. The semiconductor structure of claim 15 , wherein the second portion of the dielectric layer extends horizontally within a first uniform thickness along the vertical direction.
19. The semiconductor structure of claim 18 , wherein the spacer oxide layer has a second uniform thickness along the vertical direction.
20. The semiconductor structure of claim 15 , wherein a top surface of the dielectric layer is located within a same horizontal plane as a top surface of the second source/drain region and as a top surface of the gate electrode.