Hard mask and preparation method thereof, preparation method of Josephson junction, and superconducting circuit
A hard mask includes a silicon oxide layer provided on a bare silicon wafer; and a silicon nitride layer provided on the silicon oxide layer, wherein the silicon nitride is provided with a first pattern, the silicon oxide layer is provided with a second pattern corresponding to the first pattern, the first pattern and the second pattern have different shapes, and the first pattern and the second pattern are configured to assist in forming a Josephson junction on the bare silicon wafer.
1. A hard mask, comprising:
a silicon oxide layer provided on a bare silicon wafer; and
a silicon nitride layer provided on the silicon oxide layer, wherein:
the silicon nitride is provided with a first pattern,
the silicon oxide layer is provided with a second pattern corresponding to the first pattern,
the first pattern and the second pattern have different shapes,
the first pattern and the second pattern are in different directions and form an overlapping structure, and
the first pattern and the second pattern are configured to assist in forming a Josephson junction on the bare silicon wafer.
2. The hard mask of claim 1 , further comprising:
an image transmission layer provided on the silicon nitride layer, the image transmission layer being provided with a third pattern configured to assist in forming the first pattern corresponding to the third pattern on the silicon nitride.
3. The hard mask of claim 2 , wherein the image transmission layer is formed by a chromium material.
4. The hard mask of claim 2 , wherein thickness of the image transmission layer is greater than or equal to 15 nanometers and smaller than or equal to 50 nanometers.
5. The hard mask of claim 2 , wherein a line width size of the third pattern is the same as a line width size of the first pattern.
6. The hard mask of claim 2 , wherein a line width size of the first pattern, a line width size of the second pattern, and a line width size of the third pattern are greater than or equal to 100 nanometers.
7. The hard mask of claim 1 , wherein a line width size of the second pattern is greater than or equal to a line width size of the first pattern.
8. The hard mask of claim 1 , wherein thickness of the silicon oxide layer is greater than or equal to 200 nm and smaller than or equal to 800 nanometers.
9. The hard mask of claim 1 , wherein thickness of the silicon nitride layer is greater than or equal to 400 nanometers and smaller than or equal to 1,400 nanometers.