Method and device for boosting performance of FinFETs via strained spacer

1. A semiconductor device, comprising:

a first field effect transistor (FET) that includes:

a first source/drain feature and a second source/drain feature, and

a first fin sandwiched between the first source/drain feature and the second source/drain feature along a first direction; and

a second FET that includes:

a third source/drain feature and a fourth source/drain feature, and

a second fin sandwiched between the third source/drain feature and the fourth source/drain feature along the first direction,

wherein the first source/drain feature and the second source/drain feature are diamond-shaped when viewed along the first direction,

wherein the third source/drain feature and the fourth source/drain feature are bar-shaped when viewed along the first direction,

wherein the first source/drain feature is disposed between a first dielectric fin and a second dielectric fin along a second direction perpendicular to the first direction,

wherein the third source/drain feature is disposed between a third dielectric fin and a fourth dielectric fin along the second direction.

2. The semiconductor device of claim 1 ,

wherein the first FET is a p-type FET, and

wherein the second FET is an n-type FET.

3. The semiconductor device of claim 1 ,

wherein the first source/drain feature and the second source/drain feature comprise silicon germanium and a p-type dopant,

wherein the third source/drain feature and the fourth source/drain feature comprise silicon and an n-type dopant.

4. The semiconductor device of claim 1 , further comprising:

an isolation structure surrounding lower portions of the first fin and the second fin,

wherein the first dielectric fin, the second dielectric fin, the third dielectric fin, and the fourth dielectric fin extend into the isolation structure.

5. The semiconductor device of claim 1 ,

wherein a widest portion of the first source/drain feature comprises a first maximum width along the second direction,

wherein a widest portion of the third source/drain feature comprises a second maximum width along the second direction, and

wherein the first maximum width is greater than the second maximum width.

6. The semiconductor device of claim 5 ,

wherein the first dielectric fin and the second dielectric fin comprises a spacing along the second direction,

wherein the first maximum width is more than 75% of the spacing.

7. The semiconductor device of claim 5 ,

wherein the third dielectric fin and the fourth dielectric fin comprises a spacing along the second direction,

wherein the second maximum width is less than 40% of the spacing.

8. The semiconductor device of claim 1 , wherein a widest portion of the first source/drain feature is in direct contact with the first dielectric fin and the second dielectric fin.

9. A semiconductor structure, comprising:

a p-type field effect transistor (PFET) that includes:

a first source/drain feature and a second source/drain feature,

a first fin sandwiched between the first source/drain feature and the second source/drain feature along a first direction, and

a first dielectric fin and a second dielectric fin sandwiching the first source/drain feature along a second direction perpendicular to the first direction; and

an n-type FET (NFET) that includes:

a third source/drain feature and a fourth source/drain feature,

a second fin sandwiched between the third source/drain feature and the fourth source/drain feature along the first direction, and

a third dielectric fin and a fourth dielectric fin sandwiching the third source/drain feature along the second direction,

wherein a widest portion of the first source/drain feature comprises a first maximum width along the second direction,

wherein a widest portion of the third source/drain feature comprises a second maximum width along the second direction, and

wherein the first maximum width is greater than the second maximum width.

10. The semiconductor structure of claim 9 ,

wherein the first source/drain feature and the second source/drain feature are diamond-shaped when viewed along the first direction,

wherein the third source/drain feature and the fourth source/drain feature are bar-shaped when viewed along the first direction.

11. The semiconductor structure of claim 9 ,

wherein the PFET further comprises:

a first gate structure wrapping over the first fin and disposed adjacent the first source/drain feature and the second source/drain feature,

a first spacer disposed on a sidewall of the first gate structure and in contact with the first source/drain feature, and

a second spacer disposed over the first spacer,

wherein the NFET further comprises:

a second gate structure wrapping over the second fin and disposed adjacent the third source/drain feature and the fourth source/drain feature,

the first spacer disposed on a sidewall of the second gate structure and in contact with the first source/drain feature, and

a third spacer disposed over the first spacer, and

wherein a composition of the second spacer is different from a composition of the third spacer.

12. The semiconductor structure of claim 11 ,

wherein the second spacer comprises silicon oxycarbonitride,

wherein the third spacer comprises silicon nitride.

13. The semiconductor structure of claim 11 ,

wherein the first spacer has a first carbon content greater than 40%,

wherein the second spacer has a second carbon content smaller than 20%.

14. The semiconductor structure of claim 11 , wherein the third spacer exerts a tensile stress on the first fin.

15. A method, comprising:

providing a workpiece, the workpiece comprising:

a first fin in a P-type device region,

a second fin in an N-type device region,

a first gate structure over the first fin, and

a second gate structure over the second fin;

depositing a first spacer over the workpiece, including over the first and second gate structures;

depositing a second spacer over the first spacer;

selectively forming a first source/drain feature over the first fin adjacent the first gate structure;

selectively forming a second source/drain feature over the second fin adjacent the second gate structure;

replacing the second spacer in the N-type device region with a third spacer; and

annealing the third spacer to impart a tensile stress in the third spacer.

16. The method of claim 15 ,

wherein the selectively forming of the first source/drain feature comprises forming the first source/drain feature in a diamond shape,

wherein the selectively forming of the second source/drain feature comprises forming the second source/drain feature in a bar shape.

17. The method of claim 15 , wherein the replacing of the second spacer in the N-type device region comprises:

recessing the second spacer in the N-type device region; and

depositing the third spacer in the N-type device region.

18. The method of claim 15 , wherein the annealing of the third spacer comprises an anneal temperature between about 700° C. and about 850° C. and an anneal time between about 30 minutes and about 2 hours.

19. The method of claim 15 ,

wherein the selectively forming of the first source/drain feature comprises:

selectively recessing a source/drain region of the first fin, and

depositing the first source/drain feature over the recessed source/drain region of the first fin,

wherein the selectively forming of the second source/drain feature comprises:

after the depositing of the first source/drain feature, selectively recessing a source/drain region of the second fin, and

depositing the second source/drain feature over the recessed source/drain region of the second fin.

20. The method of claim 19 , wherein the selectively depositing the first source/drain feature comprises a process temperature greater than 600° C. such that the deposition of the first source/drain feature on all crystal planes are substantially the same.