Electronic device
According to one embodiment, the interconnect layer includes a fourth conductive member and a fifth conductive member. The fourth conductive member is provided between the first region of the first chip and the third region of the second chip. The fourth conductive member connects the first conductive member of the first chip and the second conductive member of the second chip. The fifth conductive member is provided between the second region of the first chip and the fifth region of the third chip. The fifth conductive member connects the first conductive member of the first chip and the third conductive member of the third chip. The first chip is provided between the first terminal and the second terminal.
1. An electronic device, comprising:
two or more first chips, one first chip including an interconnect member;
three or more chips including at least one second chip and at least one third chip, the second chip including a second conductive member, the third chip including a third conductive member, the second conductive member of the second chip being electrically connected to the third conductive member of the third chip via the interconnect member of the one first chip; and
an interconnect layer provided between the one first chip and the second chip, and between the one first chip and the third chip, the interconnect layer being electrically connected to the interconnect member, the second conductive member, and the third conductive member.
2. The device according to claim 1 , wherein the one first chip includes a memory element.
3. The device according to claim 1 , wherein the second chip includes a logic element.
4. The device according to claim 1 , wherein the third chip includes a memory element.
5. The device according to claim 1 , wherein the second chip includes a logic element, and the third chip includes a memory element.
6. The device according to claim 1 , further comprising a resin portion covering the second chip and the third chip.
7. The device according to claim 1 , wherein the one first chip does not include a substrate.
8. An electronic device, comprising:
a first chip including a first region and a second region;
a second chip including a third region and a fourth region; and
a third chip including a fifth region and a sixth region; and
an interconnect layer provided between the first chip and the second chip, and between the first chip and the third chip,
wherein the interconnect layer includes:
an insulating layer which is provided between the first region of the first chip and the third region of the second chip, and between the second region of the first chip and the fifth region of the third chip;
a first conductive member which is provided between the first region of the first chip and the third region of the second chip; and
a second conductive member which is provided between the second region of the first chip and the fifth region of the third chip,
wherein the second chip and the third chip are connected to each other via an optical waveguide on the first chip, and
wherein the third region toward to the first region is aligned with a first direction, and the fifth region toward to the second region is aligned with the first direction, the first direction crossing a second direction from the second chip toward the third chip.
9. An electronic device, comprising:
two or more second chips, each second chip including a second conductive member, and an artificial neuron;
a third chip including a third conductive member, and a memory element shared by at least two second chips; and
a first chip including an interconnect member connected to the second conductive member of one second chip and the third conductive member of the third chip,
the second conductive member of the one second chip being electrically connected to the third conductive member of the third chip,
an input/output information and a connection information between the artificial neurons being stored in the memory element of the third chip, and the one second chip executing calculation processing based on the information stored in the memory element of the third chip.
10. The device according to claim 9 , further comprising an interconnect layer provided between the first chip and the one second chip, and between the first chip and the third chip, the interconnect layer being electrically connected to the interconnect member, the second conductive member, and the third conductive member.
11. The device according to claim 10 , further comprising a first terminal and a second terminal, the first terminal and the second terminal being electrically connected to the interconnect layer, the first chip being provided between the first terminal and the second terminal.
12. The device according to claim 11 , wherein the artificial neuron is composed of a logic element.
13. The device according to claim 11 , further comprising a resin portion covering the one second chip and the third chip.
14. The device according to claim 11 , wherein two or more first chips, two or more second chips, and two or more third chips are arranged in a grid tile structure.
15. The device according to claim 11 , wherein the first chip does not include a substrate.
16. The device according to claim 10 , wherein the artificial neuron is composed of a logic element.
17. The device according to claim 10 , further comprising a resin portion covering the one second chip and the third chip.
18. The device according to claim 10 , wherein two or more first chips, two or more second chips, and two or more third chips are arranged in a grid tile structure.
19. The device according to claim 10 , wherein the first chip does not include a substrate.