Package-on-package (PoP) semiconductor package and electronic system including the same
A package-on-package (PoP) semiconductor package includes an upper package and a lower package. The lower package includes a first semiconductor device in a first area, a second semiconductor device in a second area, and a command-and-address vertical interconnection, a data input-output vertical interconnection, and a memory management vertical interconnection adjacent to the first area.
1. A package-on-package (PoP) semiconductor package, comprising:
an upper package including:
an upper package substrate, and
a memory device on the upper package substrate, the memory device including memory chips that are vertically stacked; and
a lower package including:
a first semiconductor device in a first area,
a second semiconductor device in a second area, and
a command-and-address (CA) vertical interconnection, a data input-output vertical interconnection, and a memory management vertical interconnection,
wherein at least one of the CA vertical interconnection, the data input-output vertical interconnection, and the memory management vertical interconnection is between the first semiconductor device and the second semiconductor device.
2. The PoP semiconductor package as claimed in claim 1 , wherein the upper package further includes a memory controller configured to control the memory device in accordance with a control of the first semiconductor device of the lower package.
3. The PoP semiconductor package as claimed in claim 2 , wherein the memory controller is laterally adjacent to the memory device.
4. The PoP semiconductor package as claimed in claim 2 , wherein:
the upper package includes a non-volatile memory device, and
the non-volatile memory device is to transmit CA signals to and receive CA signals from the first semiconductor device via the CA vertical interconnection.
5. The PoP semiconductor package as claimed in claim 4 , wherein the non-volatile memory device is to transmit data to and receive data from the first semiconductor device via the data input-output vertical interconnection.
6. The PoP semiconductor package as claimed in claim 1 , wherein at least one of the CA vertical interconnection and the memory management vertical interconnection is between the first semiconductor device and the second semiconductor device, and the data input-output vertical interconnection is not between the first semiconductor device and the second semiconductor device.
7. The PoP semiconductor package as claimed in claim 6 , wherein:
the first semiconductor device includes a first side surface and a second side surface parallel to the first side surface, the second side surface facing the second semiconductor device, and
the data input-output vertical interconnection is adjacent to the first side surface.
8. The PoP semiconductor package as claimed in claim 1 , wherein:
the lower package further includes a power vertical interconnection, a ground vertical interconnection, and a dummy vertical interconnection, and
the power vertical interconnection, the ground vertical interconnection, and the dummy vertical interconnection are adjacent to the second semiconductor device.
9. The PoP semiconductor package as claimed in claim 8 , wherein at least one of the ground vertical interconnection and the power vertical interconnection is adjacent to a first side surface of the second semiconductor device opposite to a second side surface of the second semiconductor device, the second side surface of the second semiconductor device facing the first semiconductor device.
10. The PoP semiconductor package as claimed in claim 1 , wherein the lower package includes an upper redistribution layer and a lower redistribution layer which are respectively adjacent to an upper surface and a lower surface thereof.
11. A package-on-package (PoP) semiconductor package, comprising:
an upper package including:
an upper package substrate, and
a memory device on the upper package substrate, the memory device including a first memory chip and a second memory chip that are vertically stacked, and the memory device being electrically connected to the upper package substrate via a bonding wire; and
a lower package including:
a lower package substrate having a first area and a second area,
a first semiconductor device in the first area,
a second semiconductor device in the second area, and
a command-and-address (CA) vertical interconnection, a data input-output vertical interconnection, and a memory management vertical interconnection,
wherein at least one of the CA vertical interconnection, the data input-output vertical interconnection, and the memory management vertical interconnection is between the first semiconductor device and the second semiconductor device.
12. The PoP semiconductor package as claimed in claim 11 , wherein the first memory chip and the second memory chip are electrically connected to each other by a through-silicon via (TSV).
13. The PoP semiconductor package as claimed in claim 11 , wherein the upper package further includes a memory controller configured to control the memory device in accordance with a control of the first semiconductor device of the lower package.
14. The PoP semiconductor package as claimed in claim 11 , wherein:
the first semiconductor device includes a first side surface and a second side surface parallel to the first side surface, the second side surface facing the second semiconductor device,
the data input-output vertical interconnection is adjacent to the first side surface, and
the memory management vertical interconnection is between the first semiconductor device and the second semiconductor device, and the CA vertical interconnection is adjacent to a third side surface of the first semiconductor device, the third side surface being between the first side surface and the second side surface.
15. The PoP semiconductor package as claimed in claim 11 , wherein:
the first semiconductor device includes a first side surface and a second side surface parallel to the first side surface, the second side surface facing the second semiconductor device,
the data input-output vertical interconnection is adjacent to the first side surface, and
the CA vertical interconnection is between the first semiconductor device and the second semiconductor device, and the memory management vertical interconnection is adjacent to a third side surface of the first semiconductor device, the third side surface being between the first side surface and the second side surface.
16. The PoP semiconductor package as claimed in claim 11 , wherein:
the first semiconductor device and the second semiconductor device are on the lower package substrate and are encapsulated by an encapsulation material, and
each of the CA vertical interconnection, the data input-output vertical interconnection, and the memory management vertical interconnection has a tapered shape extending through the encapsulation material.
17. A package-on-package (PoP) semiconductor package, comprising:
an upper package including:
an upper package substrate,
a memory device on a top surface the upper package substrate, the memory device including memory chips that are vertically stacked and are electrically connected to the upper package substrate via a bonding wire, and
a first encapsulation material encapsulating at least a portion of the upper package substrate and at least a portion of the memory device; and
a lower package including:
a lower package substrate having a first area and a second area,
a first semiconductor device in the first area on a top surface of the lower package substrate,
a second semiconductor device in the second area on the top surface of the lower package substrate,
a command-and-address (CA) vertical interconnection, a data input-output vertical interconnection, and a memory management vertical interconnection on the top surface of the lower package,
wherein at least one of the CA vertical interconnection, the data input-output vertical interconnection, and the memory management vertical interconnection is between the first area and the second area of the lower package substrate, and
wherein a first end of the at least one of the CA vertical interconnection, the data input-output vertical interconnection, and the memory management vertical interconnection is on the top surface of the lower package substrate between the first area and the second area of the lower package substrate, and a second end opposite to the first end of the at least one of the CA vertical interconnection, the data input-output vertical interconnection, and the memory management vertical interconnection is connected to the upper package.
18. The PoP semiconductor package as claimed in claim 17 , wherein a signal is transmitted and received between the upper package and the lower package through the at least one of the CA vertical interconnection, the data input-output vertical interconnection, and the memory management vertical interconnection.
19. The PoP semiconductor package as claimed in claim 17 , wherein the first semiconductor device is an application processor (AP) chip and the second semiconductor device is a power management integrated circuit chip.