Method of operating an integrated circuit and integrated circuit

1. A method of operating an integrated circuit, the integrated circuit including a first memory cell array, the method comprising:

writing data to each memory cell in the first memory cell array;

powering off the integrated circuit;

powering on the integrated circuit;

reading data from each memory cell in the first memory cell array in response to powering on the integrated circuit; and

determining whether to allow an authentication operation of the integrated circuit in response to reading data from each memory cell in the first memory cell array.

2. The method of claim 1 , wherein writing data to each memory cell in the first memory cell array comprises:

writing a logic 1 to each memory cell in the first memory cell array.

3. The method of claim 1 , wherein determining whether to allow the authentication operation of the integrated circuit comprises:

determining data read from at least one memory cell in the first memory cell array is not equal to data written to the at least one memory cell in the first memory cell array.

4. The method of claim 3 , wherein determining whether to allow the authentication operation of the integrated circuit further comprises:

determining a first time since powering off the integrated circuit is greater than a minimum time in response to determining the data read from the at least one memory cell in the first memory cell array is not equal to the data written to the at least one memory cell in the first memory cell array;

setting a flag to a first value in response to determining the first time since powering off the integrated circuit is greater than the minimum time; and

allowing an authentication operation of the integrated circuit in response to the flag being the first value.

5. The method of claim 4 , wherein determining whether to allow the authentication operation of the integrated circuit comprises:

determining the data read from the at least one memory cell in the first memory cell array is equal to the data written to the at least one memory cell in the first memory cell array.

6. The method of claim 5 , wherein determining whether to allow the authentication operation of the integrated circuit further comprises:

determining the first time since powering off the integrated circuit is not greater than the minimum time in response to determining the data read from the at least one memory cell in the first memory cell array is equal to the data written to the at least one memory cell in the first memory cell array;

setting the flag to a second value in response to determining the first time since powering off the integrated circuit is not greater than the minimum time, the second value being different from the first value; and

not allowing the authentication operation of the integrated circuit in response to the flag being the second value.

7. A method of operating an integrated circuit, the integrated circuit including a first memory cell array and a second memory cell array, the method comprising:

writing data to each memory cell in the first memory cell array;

writing data to each memory cell in the second memory cell array;

powering off the integrated circuit;

powering on the integrated circuit;

reading data from each memory cell in the first memory cell array in response to powering on the integrated circuit;

reading data from each memory cell in the second memory cell array in response to powering on the integrated circuit; and

determining whether to allow an authentication operation of the integrated circuit in response to reading data from each memory cell in at least the first memory cell array or the second memory cell array.

8. The method of claim 7 , wherein determining whether to allow the authentication operation of the integrated circuit in response to reading data from each memory cell in the first memory cell array comprises:

determining whether data read from at least one memory cell in the first memory cell array is equal to data written to the at least one memory cell in the first memory cell array.

9. The method of claim 8 , wherein determining whether the data read from the at least one memory cell in the first memory cell array is equal to the data written to the at least one memory cell in the first memory cell array comprises:

determining the data read from the at least one memory cell in the first memory cell array is equal to the data written to the at least one memory cell in the first memory cell array.

10. The method of claim 9 , wherein determining whether to allow the authentication operation of the integrated circuit in response to reading data from each memory cell in the first memory cell array further comprises:

determining a first time since powering off the integrated circuit is not greater than a minimum time in response to determining the data read from the at least one memory cell in the first memory cell array is equal to the data written to the at least one memory cell in the first memory cell array;

setting a first flag to a first value in response to determining the first time since powering off the integrated circuit is not greater than the minimum time; and

not allowing the authentication operation of the integrated circuit in response to the first flag being the first value.

11. The method of claim 10 , wherein determining whether to allow the authentication operation of the integrated circuit in response to reading data from each memory cell in the first memory cell array further comprises:

waiting until the data read from the at least one memory cell in the first memory cell array is not equal to the data written to the at least one memory cell in the first memory cell array;

determining the first time since powering off the integrated circuit is greater than the minimum time in response to determining the data read from the at least one memory cell in the first memory cell array is not equal to the data written to the at least one memory cell in the first memory cell array;

setting the first flag to a second value in response to determining the first time since powering off the integrated circuit is greater than the minimum time, the second value being different from the first value; and

allowing the authentication operation of the integrated circuit in response to the first flag being the second value.

12. The method of claim 8 , wherein determining whether the data read from the at least one memory cell in the first memory cell array is equal to the data written to the at least one memory cell in the first memory cell array comprises:

determining the data read from the at least one memory cell in the first memory cell array is not equal to the data written to the at least one memory cell in the first memory cell array.

13. The method of claim 12 , wherein determining whether to allow the authentication operation of the integrated circuit in response to reading data from the second memory cell array comprises:

determining whether data read from at least one memory cell in the second memory cell array is equal to data written to the at least one memory cell in the second memory cell array in response to determining the data read from the at least one memory cell in the first memory cell array is not equal to the data written to the at least one memory cell in the first memory cell array.

14. The method of claim 13 , wherein determining whether the data read from the at least one memory cell in the second memory cell array is equal to the data written to the at least one memory cell in the second memory cell array comprises:

determining the data read from the at least one memory cell in the second memory cell array is not equal to the data written to the at least one memory cell in the second memory cell array.

15. The method of claim 14 , wherein determining whether to allow the authentication operation of the integrated circuit in response to reading data from the second memory cell array further comprises:

determining a first time since powering off the integrated circuit is greater than a minimum time in response to determining the data read from the at least one memory cell in the second memory cell array is not equal to the data written to the at least one memory cell in the second memory cell array;

setting a first flag to a first value in response to determining the first time since powering off the integrated circuit is greater than the minimum time; and

allowing the authentication operation of the integrated circuit in response to the first flag being the first value.

16. The method of claim 15 , wherein determining whether the data read from the at least one memory cell in the second memory cell array is equal to the data written to the at least one memory cell in the second memory cell array comprises:

determining the data read from the at least one memory cell in the second memory cell array is equal to the data written to the at least one memory cell in the second memory cell array.

17. The method of claim 16 , wherein determining whether to allow the authentication operation of the integrated circuit in response to reading data from the second memory cell array further comprises:

determining the first time since powering off the integrated circuit is not greater than the minimum time in response to determining the data read from the at least one memory cell in the second memory cell array is equal to the data written to the at least one memory cell in the second memory cell array;

setting the first flag to a second value in response to determining the first time since powering off the integrated circuit is not greater than the minimum time, the second value being different from the first value; and

not allowing the authentication operation of the integrated circuit in response to the first flag being the second value.

18. The method of claim 7 , wherein

writing data to each memory cell in the first memory cell array comprises:

writing a logic 1 to each memory cell in the first memory cell array; and

writing data to each memory cell in the second memory cell array comprises:

writing the logic 1 to each memory cell in the second memory cell array.

19. A method of operating an integrated circuit, the integrated circuit including a first memory cell array, the method comprising:

writing data to each memory cell in the first memory cell array, wherein writing data to each memory cell in the first memory cell array comprises:

writing a logic 1 to each memory cell in the first memory cell array,

disconnecting the integrated circuit from a supply voltage;

connecting the integrated circuit to the supply voltage;

reading data from each memory cell in the first memory cell array in response to disconnecting the integrated circuit from the supply voltage; and

determining whether to allow an authentication operation of the integrated circuit in response to reading data from each memory cell in the first memory cell array.

20. The method of claim 19 , determining whether to allow the authentication operation of the integrated circuit comprises:

determining data read from a first memory cell in the first memory cell array is not equal to data written to the first memory cell in the first memory cell array.