Semiconductor devices and method for forming the same
A method includes forming a transistor over a front side of a substrate, in which the transistor comprises a channel region, a gate region over the channel region, and source/drain regions on opposite sides of the gate region; forming a front-side interconnect structure over the transistor, wherein the front-side interconnect structure includes a dielectric layer and conductive features; and bonding the front-side interconnect structure to a carrier substrate via a bonding layer, in which the bonding layer is between the front-side interconnect structure and the carrier substrate, and the bonding layer has a higher thermal conductivity than the dielectric layer of the front-side interconnect structure.
1. A method, comprising:
forming a transistor over a front side of a substrate, wherein the transistor comprises a channel region, a gate region over the channel region, and epitaxial source/drain structures on opposite sides of the gate region;
forming a front-side interconnect structure over the transistor, wherein the front-side interconnect structure comprises a dielectric layer and conductive features;
bonding the front-side interconnect structure to a carrier substrate via a bonding layer, wherein the bonding layer is between the front-side interconnect structure and the carrier substrate and the bonding layer is made of aluminum oxide or aluminum nitride;
removing a first portion of the substrate to expose a second portion of the substrate; and
forming a backside via in the second portion of the substrate and in contact with an epitaxial plug in the substrate, wherein the backside via is electrically connected to one of the epitaxial source/drain structures through the epitaxial plug.
2. The method of claim 1 , wherein the bonding layer is formed over the front-side interconnect structure prior to bonding the front-side interconnect structure to the carrier substrate.
3. The method of claim 1 , wherein the bonding layer comprises a first layer and a second layer contacting the first layer.
4. The method of claim 3 , wherein the first layer is made of aluminum oxide, and the second layer is made of aluminum nitride.
5. The method of claim 1 , further comprising forming a backside interconnect structure over the backside of the substrate and electrically connected to the backside via.
6. The method of claim 5 , further comprising:
performing a planarization process to the backside of the substrate; and
forming backside vias in the substrate.
7. A method, comprising:
forming a transistor over a front side of a substrate, wherein the transistor comprises a channel region, a gate structure over the channel region, and source/drain structures on opposite sides of the gate structure;
forming a front-side interconnect structure over the transistor;
depositing a thermal conductive layer over the front-side interconnect structure, wherein the thermal conductive layer is made of aluminum oxide or aluminum nitride;
bonding the front-side interconnect structure to a carrier substrate via the thermal conductive layer;
performing a planarization process to a backside of the substrate until a buried oxide layer of the substrate is exposed; and
forming a backside via in the buried oxide layer and electrically connected to the transistor.
8. The method of claim 7 , further comprising forming a backside interconnect structure over the backside of the substrate and electrically connected to the backside via.
9. The method of claim 7 , wherein the thermal conductive layer comprises a first layer in contact with the front-side interconnect structure, and a second layer over the first layer, and a thermal conductivity of the first layer is higher than a thermal conductivity of the second layer.
10. The method of claim 7 , wherein the thermal conductive layer comprises aluminum oxide or aluminum nitride.
11. The method of claim 7 , wherein the thermal conductive layer comprises a first layer in contact with the front-side interconnect structure, and a second layer over the first layer, and the first layer comprises aluminum oxide and the second layer comprises aluminum nitride.
12. The method of claim 7 , wherein the thermal conductive layer comprises a first layer in contact with the front-side interconnect structure, and a second layer over the first layer, and the first layer comprises aluminum nitride and the second layer comprises aluminum oxide.
13. A method, comprising:
forming a transistor over a front side of a substrate, wherein the transistor comprises a channel region, a gate region over the channel region, and source/drain regions on opposite sides of the gate region;
forming a front-side interconnect structure over the transistor, wherein the front-side interconnect structure comprises a dielectric layer and conductive features;
bonding the front-side interconnect structure to a carrier substrate via a bonding layer, wherein the bonding layer comprises:
a first layer; and
a second layer in contact with the first layer, wherein the first layer is made of aluminum oxide, and the second layer is made of aluminum nitride, and wherein the bonding layer is in contact with at least one of the conductive features of the front-side interconnect structure
performing a planarization process to a backside of the substrate until a buried oxide layer of the substrate is exposed; and
forming a backside via in the buried oxide layer and electrically connected to the transistor.
14. The method of claim 13 , further comprising forming a backside interconnect structure electrically connected with the backside via.
15. The method of claim 13 , wherein the carrier substrate is made of a semiconductor material and is in contact with the second layer of the bonding layer.
16. The method of claim 13 , wherein the first layer is in contact with the front-side interconnect structure, and the second layer is in contact with the carrier substrate.
17. The method of claim 13 , wherein the first layer is in contact with the carrier substrate, and the second layer is in contact with the front-side interconnect structure.
18. The method of claim 13 , wherein a thermal conductivity of a bulk material of the second layer is in a range from about 280 W/m*K to about 290 W/m*K.
19. The method of claim 13 , further comprising:
performing a planarization process to a backside of the substrate until a buried oxide layer of the substrate is exposed; and
forming a backside interconnect structure over the buried oxide layer.
20. The method of claim 1 , wherein removing the first portion of the substrate comprises performing a planarization process to a backside of the substrate until the second portion of the substrate is exposed, wherein the second portion of the substrate is a buried oxide layer.