Memory device including memory cells and edge cells

1. A memory device, comprising:

an array of memory cells used for data storage;

a plurality of first edge cells not used for data storage; and

a plurality of second edge cells not used for data storage, wherein

the plurality of first edge cells and the plurality of second edge cells are arranged respectively at two opposite sides of the array of memory cells, and

at least one edge cell, among the plurality of first edge cells and the plurality of second edge cells, comprises a circuit configured for controlling the array of memory cells to enter or exit a power down mode.

2. The memory device of claim 1 , wherein each edge cell of the plurality of first edge cells and the plurality of second edge cells comprises:

a pair of transistors whose gates are coupled to each other and coupled to a word line of the edge cell.

3. The memory device of claim 2 , wherein:

the pair of transistors are p-type metal-oxide-semiconductor (PMOS) transistors;

sources of the pair of transistors are coupled to a positive power supply voltage; and

drains of the pair of transistors are coupled to a power header supply voltage for controlling the array of memory cells to enter or exit the power down mode.

4. The memory device of claim 3 , wherein:

when the word line of the edge cell switches to a logic high power level, the array of memory cells enters the power down mode; and

when the word line of the edge cell switches to a logic low power level, the array of memory cells exits the power down mode.

5. The memory device of claim 2 , wherein:

the pair of transistors are n-type metal-oxide-semiconductor (NMOS) transistors;

sources of the pair of transistors are coupled to a power footer supply voltage for controlling the array of memory cells to enter or exit the power down mode; and

drains of the pair of transistors are coupled to a negative power supply voltage.

6. The memory device of claim 5 , wherein:

when the word line of the edge cell switches to a logic low power level, the array of memory cells enters the power down mode; and

when the word line of the edge cell switches to a logic high power level, the array of memory cells exits the power down mode.

7. The memory device of claim 2 , wherein voltages of the word lines of the plurality of first edge cells and the plurality of second edge cells are controlled by a common power management signal.

8. The memory device of claim 1 , wherein:

each first edge cell of the plurality of first edge cells comprises a pair of PMOS transistors whose gates are coupled to each other and coupled to a word line of the first edge cell; and

each second edge cell of the plurality of second edge cells comprises a pair of NMOS transistors whose gates are coupled to each other and coupled to a word line of the second edge cell.

9. The memory device of claim 7 , wherein:

sources of the pair of PMOS transistors are coupled to a positive power supply voltage of the first edge cell;

drains of the pair of PMOS transistors are coupled to a power header supply voltage of the first edge cell;

sources of the pair of NMOS transistors are coupled to a power footer supply voltage of the second edge cell; and

drains of the pair of NMOS transistors are coupled to a negative power supply voltage of the second edge cell.

10. The memory device of claim 7 , wherein:

a voltage of the word line of each first edge cell is controlled by a power management signal and a delay circuit; and

a voltage of the word line of each second edge cell is controlled by the power management signal and an invertor circuit.

11. A static random access memory (SRAM) chip, comprising:

an array of SRAM cells used for data storage;

a plurality of first edge cells not used for data storage; and

a plurality of second edge cells not used for data storage, wherein

the plurality of first edge cells and the plurality of second edge cells are arranged respectively at two opposite sides of the array of SRAM cells, and

at least one edge cell, among the plurality of first edge cells and the plurality of second edge cells, comprises a power switch configured for controlling a power supply to the array of SRAM cells.

12. The SRAM chip of claim 11 , wherein each edge cell of the plurality of first edge cells and the plurality of second edge cells comprises:

a pair of transistors whose gates are coupled to each other and coupled to a word line of the edge cell.

13. The SRAM chip of claim 12 , wherein:

the pair of transistors are p-type metal-oxide-semiconductor (PMOS) transistors;

sources of the pair of transistors are coupled to a positive power supply voltage;

drains of the pair of transistors are coupled to a power header supply voltage;

when the word line of the edge cell switches to a logic high power level, the array of SRAM cells enters a power down mode; and

when the word line of the edge cell switches to a logic low power level, the array of SRAM cells exits the power down mode.

14. The SRAM chip of claim 12 , wherein:

the pair of transistors are n-type metal-oxide-semiconductor (NMOS) transistors;

sources of the pair of transistors are coupled to a power footer supply voltage;

drains of the pair of transistors are coupled to a negative power supply voltage;

when the word line of the edge cell switches to a logic low power level, the array of SRAM cells enters a power down mode; and

when the word line of the edge cell switches to a logic high power level, the array of SRAM cells exits the power down mode.

15. The SRAM chip of claim 12 , wherein voltages of the word lines of the plurality of first edge cells and the plurality of second edge cells are controlled by a common power management signal.

16. The SRAM chip of claim 11 , wherein:

each first edge cell of the plurality of first edge cells comprises a pair of PMOS transistors whose gates are coupled to each other and coupled to a word line of the first edge cell;

sources of the pair of PMOS transistors are coupled to a positive power supply voltage of the first edge cell;

drains of the pair of PMOS transistors are coupled to a power header supply voltage of the first edge cell;

each second edge cell of the plurality of second edge cells comprises a pair of NMOS transistors whose gates are coupled to each other and coupled to a word line of the second edge cell;

sources of the pair of NMOS transistors are coupled to a power footer supply voltage of the second edge cell; and

drains of the pair of NMOS transistors are coupled to a negative power supply voltage of the second edge cell.

17. The SRAM chip of claim 16 , wherein:

a voltage of the word line of each first edge cell is controlled by a power management signal and a delay circuit; and

a voltage of the word line of each second edge cell is controlled by the power management signal and an invertor circuit.

18. A method for operating a static random access memory (SRAM) chip that includes: an array of SRAM cells and a plurality of edge cells, comprising:

applying a logic high power to a sleep signal to generate an activated sleep signal;

shifting a first word line, coupled to a power header edge cell of the plurality of edge cells, from a logic low power to a logic high power based on the activated sleep signal;

turning off a pair of PMOS transistors in the power header edge cell in response to shifting the first word line;

shifting a second word line, coupled to a power footer edge cell of the plurality of edge cells, from a logic high power to a logic low power based on the activated sleep signal;

turning off a pair of NMOS transistors in the power footer edge cell in response to shifting the second word line; and

switching the array of SRAM cells from a normal power mode to a power down mode based on turning off the PMOS and NMOS transistors.

19. The method of claim 18 , wherein:

the power header edge cell and the power footer edge cell are arranged respectively at two opposite sides of the array of SRAM cells;

gates of the pair of PMOS transistors are coupled to each other and coupled to the word line;

sources of the pair of PMOS transistors are coupled to a positive power supply voltage;

drains of the pair of PMOS transistors are coupled to a power supply to the array of SRAM cells;

gates of the pair of NMOS transistors are coupled to each other and coupled to the word line;

sources of the pair of NMOS transistors are coupled to a power supply to the array of SRAM cells; and

drains of the pair of NMOS transistors are coupled to a negative power supply voltage.

20. The method of claim 18 , further comprising:

applying a logic low power to the sleep signal to generate a deactivated sleep signal;

shifting the first word line, coupled to the power header edge cell of the plurality of edge cells, from a logic high power to a logic low power based on the deactivated sleep signal;

turning on the pair of PMOS transistors in the power header edge cell;

shifting the second word line, coupled to the power footer edge cell of the plurality of edge cells, from a logic low power to a logic high power based on the deactivated sleep signal;

turning on the pair of NMOS transistors in the power footer edge cell; and

switching the array of SRAM cells from the power down mode to the normal power mode based on turning on the PMOS and NMOS transistors.