Electronic circuit and method for clock skew-calibration
The electronic circuit for multiphase clock skew calibration of at least one example embodiment provides a novel low power solution to detect clock skew errors with very high accuracy, of the order of a few femto seconds, and corrects clock skew errors and decreases and/or minimizes high frequency jitter in a data path of the electronic circuit.
1. An electronic circuit for multi-phase clock skew calibration comprising:
a filtering circuit configured to filter data output by multi-phase clock-driven serializer circuitry, and generate a differential voltage representative of skew between a plurality of input multi-phase clock signals to the serializer circuitry, wherein a polarity of the differential voltage represents the polarity of skew of the multi-phase clock signals;
discrete time integrator circuitry configured to amplify the generated differential voltage;
comparator circuitry configured to determine a divergence of the differential voltage based on the differential voltage and a desired value; and
clock-skew corrector circuitry configured to,
modify rising edge or falling edge positions of the plurality of multi-phase clock signals based on the determined divergence,
trigger the serializer circuitry to output data in accordance with the modified plurality of multi-phase clock signals, and
decrease the skew between the plurality of multi-phase clock signals.
2. The electronic circuit as claimed in claim 1 , wherein the plurality of multi-phase clock signals correspond to a half-rate or a quarter-rate serializer-configuration.
3. The electronic circuit as claimed in claim 1 , wherein the multi-phase clock-driven serializer circuitry is configured to:
receive a desired input data pattern through the plurality of multi-phase clock signals via edge-triggering;
sense the skew between the plurality of multi-phase clock signals;
output a signal having a duty cycle proportional to the skew between the plurality of multi-phase clock signals; and
iteratively calibrate an interval of the output data of the serializer circuitry to one unit interval based on the calibration of the plurality of multi-phase clock signals and thereby enable calibration within a datapath of the electronic circuit.
4. The electronic circuit as claimed in claim 3 , wherein the filtering circuit includes a low pass circuit configured to generate the differential voltage based on a duty cycle of the output data of the serializer circuitry, wherein
the generated differential voltage is a static differential voltage.
5. The electronic circuit as claimed in claim 1 , wherein the discrete time integrator circuitry is configured to:
integrate the differential voltage from a low pass filter circuit; and
generate the amplified differential voltage with a desired gain and decreased effective offset based on results of the integration; and
transmit the amplified differential voltage to the comparator circuitry.
6. The electronic circuit as claimed in claim 1 , wherein the comparator circuitry includes an auto-zero comparator circuit configured to compare the amplified differential voltage with a desired value for detecting a duty cycle.
7. The electronic circuit as claimed in claim 1 , further comprising:
control generator circuitry configured to execute a Finite State Machine (FSM) to generate control signals based on output of the comparator circuitry, the control signals denoted by a plurality of up and down codes, the control signals controlling the skew of the plurality of multi-phase clock signals.
8. The electronic circuit as claimed in claim 1 , wherein the clock-skew corrector circuitry comprises:
a pull-up transistor configured to adjust the rising edge of at least one clock signal of the plurality of multi-phase clock signals based on a first control voltage defined by the up code;
a pull-down transistor configured to adjust the falling edge of the at least one clock signal of the plurality of multi-phase clock signals based on a second control voltage defined by the down code; and
a cross coupled inverter configured to maintain a complementary nature of the plurality of multi-phase clock signals.
9. The electronic circuit as claimed in claim 1 , further comprising:
control generator circuitry configured in a negative feedback configuration to:
decrease skew between clock phases of the plurality of multi-phase clock signals;
increment upcode to cause decrementing of a duty cycle until the output of the comparator circuitry changes from a first level to a second level; and
decrement downcode to cause incrementing of a duty cycle until the output of the comparator circuitry changes from the second level to the first level.
10. An electronic circuit for multi-phase clock skew-calibration comprising:
a filtering circuit configured to filter a plurality of multi-phase clock signals, and generate a differential voltage representative of skew between the plurality of multi-phase clock signals;
discrete time integrator circuitry configured to amplify the generated differential voltage;
comparator circuitry configured to determine a divergence of the differential voltage based on the differential voltage and a desired value; and
clock-skew corrector circuitry configured to modify rising edge or falling edge positions of the plurality of multi-phase clock signals based on the determined divergence, and decrease the skew between the plurality of multi-phase clock signals.
11. A process for multi-phase clock skew-calibration in an electronic circuit comprising:
applying a desired data pattern as input to a multi-phase clock-driven serializer circuitry to determine clock skew information;
filtering data output by the multi-phase clock-driven serializer circuitry;
generating a differential voltage representative of skew between a plurality of multi-phase clock signals input to the multi-phase clock-driven serializer circuitry;
amplifying the generated differential voltage through a discrete time integration;
determining a divergence of the differential voltage based on the differential voltage and a desired value;
modifying rising edge and falling edge positions of at least one of the plurality of multi-phase clock signals through clock-skew corrector circuitry based on the determined divergence to decrease the skew between the plurality of clock signals; and
triggering the multi-phase clock-driven serializer circuitry to output data in accordance with the modified at least one clock signal.
12. The process for multi-phase clock skew-calibration in the electronic circuit as claimed in claim 11 , wherein the plurality of multi-phase clock signals correspond to a half-rate or a quarter-rate serializer-configuration.
13. The process for multi-phase clock skew-calibration in the electronic circuit as claimed in claim 11 , further comprising:
receiving the desired input data pattern through the plurality of multi-phase clock signals via edge-triggering through the multi-phase clock-driven serializer circuitry;
sensing the skew between the plurality of multi-phase clock signals through the multi-phase clock-driven serializer circuitry;
outputting a signal having a duty cycle proportional to the skew between the plurality of multi-phase clock signals through the multi-phase clock-driven serializer circuitry; and
iteratively calibrating an interval of the output data of the serializer circuitry to one unit interval based on the calibration of the plurality of multi-phase clock signals and thereby enabling calibration within a datapath of the electronic circuit through the multi-phase clock-driven serializer circuitry.
14. The process for multi-phase clock skew-calibration in the electronic circuit as claimed in claim 13 , further comprising:
generating the differential voltage based on a duty cycle of the output data of the serializer circuitry using a low pass circuit.
15. The process for multi-phase clock skew-calibration in the electronic circuit as claimed in claim 14 , wherein the generated differential voltage is a static differential voltage.
16. The process for multi-phase clock skew-calibration in the electronic circuit as claimed in claim 11 , further comprising:
integrating the differential voltage from a low pass filter circuit through a discrete time integrator circuitry;
generating the amplified differential voltage with a desired gain and decreased effective offset based on results of the integration through the discrete time integrator circuitry; and
transmitting the amplified differential voltage to comparator circuitry.
17. The process for multi-phase clock skew-calibration in the electronic circuit as claimed in claim 11 , further comprising:
comparing the amplified differential voltage with a desired value for detecting duty cycle using an auto-zero comparator circuit.
18. The process for multi-phase clock skew-calibration in the electronic circuit as claimed in claim 11 , further comprising:
executing a Finite State Machine (FSM) to generate control signals based on output of a comparator circuitry, the control signals denoted by a plurality of up and down codes, the control signals controlling the skew of the plurality of multi-phase clock signals through a control generator circuitry.
19. The process for multi-phase clock skew-calibration in the electronic circuit as claimed in claim 11 , further comprising:
adjusting the rising edge of at least one clock signal of the plurality of multi-phase clock signals based on a first control voltage defined by the up code using a pull-up transistor;
adjusting the falling edge of the at least one clock signal of the plurality of multi-phase clock signals based on a second control voltage defined by the down code using a pull-down transistor; and
maintaining a complementary nature of the plurality of multi-phase clock signals using a cross coupled inverter.
20. The process for multi-phase clock skew-calibration in the electronic circuit as claimed in claim 11 , further comprising:
decreasing skew between clock phases of the plurality of multi-phase clock signals through control generator circuitry;
incrementing upcode to cause decrementing of a duty cycle until the output of the comparator circuitry changes from a first level to a second level through the control generator circuitry; and
decrementing downcode to cause incrementing of the duty cycle until the output of comparator circuitry changes from the second level to the first level through the control generator circuitry.