Three-dimensional memory device having parallel trench type capacitor
A 3D memory device may include a logic device layer on a substrate and a memory device layer stacked on the logic device layer. The logic device layer may include logic devices disposed on the substrate. The memory device layer may include a word line stack disposed in an extension area, staircase patterns disposed in the word line stack, a dielectric layer stack in a peripheral area, and capacitors inlayed in the dielectric layer stack.
1. A three-dimensional memory device comprising:
a logic device layer on a substrate; and
a memory device layer stacked on the logic device layer,
wherein the logic device layer includes logic devices disposed on the substrate,
wherein the memory device layer includes:
a word line stack disposed in an extension area;
staircase patterns disposed in the word line stack;
a dielectric layer stack in a peripheral area; and
capacitors inlayed in the dielectric layer,
wherein the capacitors include a first capacitor having a first capacitor electrodes and a second capacitor having a second capacitor electrodes,
wherein:
the first capacitor electrodes have a first height,
the second capacitor electrodes have a second height, and
the first height is less than the second height.
2. The three-dimensional memory device of claim 1 ,
wherein:
the first capacitor electrodes include a first left capacitor electrode and a first right capacitor electrode,
the second capacitor electrodes include a second left capacitor electrode and a second right capacitor electrode,
the first left capacitor electrode and the first right capacitor electrode each have a wall-like shape in parallel with each other, and
the second left capacitor electrode and the second right capacitor electrode each have a wall-like shape in parallel with each other.
3. The three-dimensional memory device of claim 2 ,
wherein:
the capacitors further include a third capacitor having third capacitor electrodes inlayed in the dielectric layer, and
the third capacitor electrodes have a third height that is greater than the first height and less than the second height.
4. The three-dimensional memory device of claim 2 ,
wherein at least one of the second left capacitor electrode and the second right capacitor electrode of the second capacitor includes an upper portion having a first horizontal width and a lower portion having a second horizontal width, and
wherein the first horizontal width is greater than the second horizontal width.
5. The three-dimensional memory device of claim 2 , further comprising:
a planarization layer disposed on the dielectric layer; and
capacitor contacts penetrating the planarization layer to be connected to the first and second capacitor electrodes,
wherein the capacitor contacts include:
a first left capacitor contact connected to the first left capacitor electrode;
a first right capacitor contact connected to the first right capacitor electrode;
a second left capacitor contact connected to the second left capacitor electrode; and
a second right capacitor contact connected to the second right capacitor electrode.
6. The three-dimensional memory device of claim 5 , further comprising capacitor interconnections disposed on the capacitor contacts,
wherein the capacitor interconnections include:
a first capacitor interconnection connected to the first left capacitor contact,
a second capacitor interconnection connected to the second left capacitor contact; and
a common capacitor interconnection commonly connected to the first right capacitor contact and the second right capacitor contact.
7. The three-dimensional memory device of claim 1 ,
wherein each of the staircase patterns has a symmetrical shape formed by a left staircase shape and a right staircase shape.
8. The three-dimensional memory device of claim 1 ,
wherein the dielectric layer includes first insulating layers and second insulating layers alternately stacked.
9. The three-dimensional memory device of claim 8 ,
wherein the word line stack includes the first insulating layers and word lines alternately stacked.
10. The three-dimensional memory device of claim 9 ,
wherein the second insulating layers and the word lines are positioned at same levels, respectively.
11. The three-dimensional memory device of claim 1 ,
wherein the logic devices include transistors, logic interconnections, and logic via plugs.
12. A three-dimensional memory device comprising:
a substrate having an extension area and a peripheral area;
a word line stack disposed in the extension area, the word line stack including first insulating layers and word lines alternately stacked;
a plurality of staircase patterns disposed in the word line stack;
a dielectric layer stack disposed in the peripheral area; and
capacitor electrodes disposed in the dielectric layer in parallel with each other,
wherein the capacitor electrodes include left capacitor electrodes and right capacitor electrodes that are inlayed in the dielectric layer and that have a wall-like shape.
13. The three-dimensional memory device of claim 12 ,
wherein the dielectric layer including the first insulating layers and second insulating layers alternately stacked.
14. The three-dimensional memory device of claim 13 ,
wherein the left capacitor electrodes include a first left capacitor electrode and a second left capacitor electrode inlayed in the dielectric layer, the first left capacitor electrode having a first height and the second left capacitor electrode having a second height, and
wherein the first height is less than the second height.
15. The three-dimensional memory device of claim 14 ,
wherein the right capacitor electrodes include a first right capacitor electrode adjacent and parallel to the first left capacitor electrode and a second right capacitor electrode adjacent and parallel to the second left capacitor electrode.
16. A three-dimensional memory device comprising:
a logic device layer on a substrate; and
a memory device layer stacked on the logic device layer,
wherein the logic device layer includes logic devices disposed on the substrate,
wherein the memory device layer includes:
a word line stack disposed in an extension area;
a plurality of staircase patterns disposed in the word line stack;
a dielectric layer stack disposed in a peripheral area; and
a plurality of capacitors disposed in the dielectric layer,
wherein the word line stack includes first insulating layers and word lines alternately stacked,
wherein the dielectric layer includes the first insulating layers and second insulating layers alternately stacked, and
wherein the plurality of capacitors include first capacitor electrodes having a first height, second capacitor electrodes having a second height, and third capacitor electrodes having a third height.
17. The three-dimensional memory device of claim 16 ,
wherein the first capacitor electrodes include a first left capacitor electrode and a first right capacitor electrode adjacent to each other,
wherein the second capacitor electrodes include a second left capacitor electrode and a second right capacitor electrode adjacent to each other, and
wherein the third capacitor electrodes include a third left capacitor electrode and a third right capacitor electrode adjacent to each other.
18. The three-dimensional memory device of claim 17 ,
wherein the first left capacitor electrode and the first right capacitor electrode are inlayed in the dielectric layer to have a wall-like shape in parallel with each other,
wherein the second left capacitor electrode and the second right capacitor electrode are inlayed in the dielectric layer to have a wall-like shape in parallel with each other, and
wherein the third left capacitor electrode and the third right capacitor electrode are inlayed in the dielectric layer to have a wall-like shape in parallel with each other.
19. The three-dimensional memory device of claim 16 ,
wherein the third height is greater than the first height and less than the second height.